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ac: move num_sdp_interfaces into radeon_info

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Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This commit is contained in:
Marek Olšák
2019-09-12 19:00:23 -04:00
parent 2c62b461e9
commit deab3a23f6
4 changed files with 17 additions and 30 deletions
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14
src/amd/common/ac_gpu_info.c
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@@ -570,6 +570,20 @@ bool ac_query_gpu_info(int fd, void *dev_p,
} }
} }
if (info->chip_class >= GFX10) {
switch (info->family) {
case CHIP_NAVI10:
case CHIP_NAVI12:
info->num_sdp_interfaces = 16;
break;
case CHIP_NAVI14:
info->num_sdp_interfaces = 8;
break;
default:
assert(0);
}
}
return true; return true;
} }

1
src/amd/common/ac_gpu_info.h
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@@ -67,6 +67,7 @@ struct radeon_info {
bool has_out_of_order_rast; bool has_out_of_order_rast;
bool cpdma_prefetch_writes_memory; bool cpdma_prefetch_writes_memory;
uint32_t pbb_max_alloc_count; uint32_t pbb_max_alloc_count;
uint32_t num_sdp_interfaces;
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */

16
src/amd/vulkan/radv_pipeline.c
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@@ -3170,20 +3170,6 @@ radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipe
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
VkExtent2D extent = {512, 512}; VkExtent2D extent = {512, 512};
unsigned sdp_interface_count;
switch(pipeline->device->physical_device->rad_info.family) {
case CHIP_NAVI10:
case CHIP_NAVI12:
sdp_interface_count = 16;
break;
case CHIP_NAVI14:
sdp_interface_count = 8;
break;
default:
unreachable("Unhandled GFX10 chip");
}
const unsigned db_tag_size = 64; const unsigned db_tag_size = 64;
const unsigned db_tag_count = 312; const unsigned db_tag_count = 312;
const unsigned color_tag_size = 1024; const unsigned color_tag_size = 1024;
@@ -3192,7 +3178,7 @@ radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipe
const unsigned fmask_tag_count = 44; const unsigned fmask_tag_count = 44;
const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends; const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
const unsigned pipe_count = MAX2(rb_count, sdp_interface_count); const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count; const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count; const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;

16
src/gallium/drivers/radeonsi/si_state_binning.c
View File

@@ -313,20 +313,6 @@ static void gfx10_get_bin_sizes(struct si_context *sctx,
struct uvec2 *color_bin_size, struct uvec2 *color_bin_size,
struct uvec2 *depth_bin_size) struct uvec2 *depth_bin_size)
{ {
unsigned num_sdp_interfaces = 0;
switch (sctx->family) {
case CHIP_NAVI10:
case CHIP_NAVI12:
num_sdp_interfaces = 16;
break;
case CHIP_NAVI14:
num_sdp_interfaces = 8;
break;
default:
assert(0);
}
const unsigned ZsTagSize = 64; const unsigned ZsTagSize = 64;
const unsigned ZsNumTags = 312; const unsigned ZsNumTags = 312;
const unsigned CcTagSize = 1024; const unsigned CcTagSize = 1024;
@@ -335,7 +321,7 @@ static void gfx10_get_bin_sizes(struct si_context *sctx,
const unsigned FcReadTags = 44; const unsigned FcReadTags = 44;
const unsigned num_rbs = sctx->screen->info.num_render_backends; const unsigned num_rbs = sctx->screen->info.num_render_backends;
const unsigned num_pipes = MAX2(num_rbs, num_sdp_interfaces); const unsigned num_pipes = MAX2(num_rbs, sctx->screen->info.num_sdp_interfaces);
const unsigned depthBinSizeTagPart = ((ZsNumTags * num_rbs / num_pipes) * (ZsTagSize * num_pipes)); const unsigned depthBinSizeTagPart = ((ZsNumTags * num_rbs / num_pipes) * (ZsTagSize * num_pipes));
const unsigned colorBinSizeTagPart = ((CcReadTags * num_rbs / num_pipes) * (CcTagSize * num_pipes)); const unsigned colorBinSizeTagPart = ((CcReadTags * num_rbs / num_pipes) * (CcTagSize * num_pipes));