intel/fs/xehp: Teach SWSB pass about the exec pipeline of FS_OPCODE_PACK_HALF_2x16_SPLIT.

This virtual instruction is translated into multiple half float
physical instructions, even though its destination is typically of
integer type, which prevents the software scoreboard pass from
inferring the correct execution pipeline for the virtual instruction
on XeHP+ platforms.  Teach the SWSB lowering pass about this
inconsistency between the IR and physical instruction types.

Fixes among other tests:

dEQP-GLES31.functional.shaders.builtin_functions.pack_unpack.packhalf2x16_compute

Fixes: d4537770bb ("intel/fs: Add helper functions inferring sync and exec pipeline of an instruction.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5685
Reported-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14002>

src/intel/compiler/brw_fs_scoreboard.cpp

@@ -122,6 +122,8 @@ namespace {
       else if (inst->opcode == SHADER_OPCODE_BROADCAST &&
                !devinfo->has_64bit_float && type_sz(t) >= 8)
          return TGL_PIPE_INT;
+      else if (inst->opcode == FS_OPCODE_PACK_HALF_2x16_SPLIT)
+         return TGL_PIPE_FLOAT;
       else if (type_sz(inst->dst.type) >= 8 || type_sz(t) >= 8 ||
                is_dword_multiply)
          return TGL_PIPE_LONG;