pan/bi: Interpret register allocation results
Once LCRA has run, we have a map from IR indices to byte offsets into the register file, so we need to "install" these results, rewriting the IR to use native registers and fixing up writemasks/swizzles to substitute vectorization for adjacent registers (for LCRA, we're modeling in terms of real vectors). Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
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@@ -89,6 +89,99 @@ bi_allocate_registers(bi_context *ctx, bool *success)
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return l;
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return l;
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}
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}
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static unsigned
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bi_reg_from_index(struct lcra_state *l, unsigned index, unsigned offset)
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{
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/* Did we run RA for this index at all */
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if (index >= l->node_count)
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return index;
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/* LCRA didn't bother solving this index (how lazy!) */
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signed solution = l->solutions[index];
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if (solution < 0)
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return index;
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solution += offset;
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assert((solution & 0x3) == 0);
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unsigned reg = solution / 4;
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return BIR_INDEX_REGISTER | reg;
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}
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static void
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bi_adjust_src_ra(bi_instruction *ins, struct lcra_state *l, unsigned src)
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{
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if (ins->src[src] >= l->node_count)
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return;
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bool vector = (bi_class_props[ins->type] & BI_VECTOR);
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unsigned offset = 0;
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if (vector) {
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/* TODO: Do we do anything here? */
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} else {
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/* Use the swizzle as component select */
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nir_alu_type T = ins->src_types[src];
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unsigned size = nir_alu_type_get_type_size(T);
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unsigned bytes = (MAX2(size, 8) / 8);
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unsigned comps_per_reg = 4 / bytes;
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unsigned components = bi_get_component_count(ins);
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for (unsigned i = 0; i < components; ++i) {
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unsigned off = ins->swizzle[src][i] / comps_per_reg;
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off *= 4; /* 32-bit registers */
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/* We can't cross register boundaries in a swizzle */
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if (i == 0)
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offset = off;
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else
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assert(off == offset);
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ins->swizzle[src][i] %= comps_per_reg;
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}
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}
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ins->src[src] = bi_reg_from_index(l, ins->src[src], offset);
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}
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static void
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bi_adjust_dest_ra(bi_instruction *ins, struct lcra_state *l)
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{
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if (ins->dest >= l->node_count)
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return;
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bool vector = (bi_class_props[ins->type] & BI_VECTOR);
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unsigned offset = 0;
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if (!vector) {
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/* Look at the writemask to get an offset, specifically the
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* trailing zeros */
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unsigned tz = __builtin_ctz(ins->writemask);
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/* Recall writemask is one bit per byte, so tz is in bytes */
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unsigned regs = tz / 4;
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offset = regs * 4;
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/* Adjust writemask to compensate */
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ins->writemask >>= offset;
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}
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ins->dest = bi_reg_from_index(l, ins->dest, offset);
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}
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static void
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bi_install_registers(bi_context *ctx, struct lcra_state *l)
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{
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bi_foreach_instr_global(ctx, ins) {
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bi_adjust_dest_ra(ins, l);
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bi_foreach_src(ins, s)
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bi_adjust_src_ra(ins, l, s);
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}
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}
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void
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void
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bi_register_allocate(bi_context *ctx)
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bi_register_allocate(bi_context *ctx)
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{
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{
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@@ -108,5 +201,7 @@ bi_register_allocate(bi_context *ctx)
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assert(success);
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assert(success);
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} while(!success);
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} while(!success);
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bi_install_registers(ctx, l);
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lcra_free(l);
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lcra_free(l);
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}
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}
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@@ -864,6 +864,7 @@ bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned
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bi_print_shader(ctx, stdout);
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bi_print_shader(ctx, stdout);
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bi_schedule(ctx);
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bi_schedule(ctx);
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bi_register_allocate(ctx);
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bi_register_allocate(ctx);
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bi_print_shader(ctx, stdout);
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ralloc_free(ctx);
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ralloc_free(ctx);
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}
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}
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