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amd: update amdgpu_drm.h

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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986>
This commit is contained in:
Pierre-Eric Pelloux-Prayer
2023-03-17 14:42:19 +01:00
committed by Marge Bot
parent 171d316402
commit dc5a9e176c
2 changed files with 26 additions and 0 deletions
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18
include/drm-uapi/amdgpu_drm.h
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@@ -592,6 +592,7 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a
struct drm_amdgpu_cs_chunk { struct drm_amdgpu_cs_chunk {
__u32 chunk_id; __u32 chunk_id;
@@ -708,6 +709,15 @@ struct drm_amdgpu_cs_chunk_data {
}; };
}; };
#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1
struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
__u64 shadow_va;
__u64 csa_va;
__u64 gds_va;
__u64 flags;
};
/* /*
* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
* *
@@ -1126,6 +1136,14 @@ struct drm_amdgpu_info_device {
__u64 mall_size; /* AKA infinity cache */ __u64 mall_size; /* AKA infinity cache */
/* high 32 bits of the rb pipes mask */ /* high 32 bits of the rb pipes mask */
__u32 enabled_rb_pipes_mask_hi; __u32 enabled_rb_pipes_mask_hi;
/* shadow area size for gfx11 */
__u32 shadow_size;
/* shadow area base virtual alignment for gfx11 */
__u32 shadow_alignment;
/* context save area size for gfx11 */
__u32 csa_size;
/* context save area base virtual alignment for gfx11 */
__u32 csa_alignment;
}; };
struct drm_amdgpu_info_hw_ip { struct drm_amdgpu_info_hw_ip {

8
src/amd/common/ac_gpu_info.c
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@@ -196,6 +196,14 @@ struct drm_amdgpu_info_device {
uint64_t mall_size; /* AKA infinity cache */ uint64_t mall_size; /* AKA infinity cache */
/* high 32 bits of the rb pipes mask */ /* high 32 bits of the rb pipes mask */
uint32_t enabled_rb_pipes_mask_hi; uint32_t enabled_rb_pipes_mask_hi;
/* shadow area size for gfx11 */
uint32_t shadow_size;
/* shadow area base virtual alignment for gfx11 */
uint32_t shadow_alignment;
/* context save area size for gfx11 */
uint32_t csa_size;
/* context save area base virtual alignment for gfx11 */
uint32_t csa_alignment;
}; };
struct drm_amdgpu_info_hw_ip { struct drm_amdgpu_info_hw_ip {
uint32_t hw_ip_version_major; uint32_t hw_ip_version_major;