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gallium: Drop the unused RFL opcode.

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Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
This commit is contained in:
Eric Anholt
2014-11-12 14:32:13 -08:00
parent 8c822b1e91
commit dc00b382b5
10 changed files with 5 additions and 98 deletions
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3
src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
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@@ -715,9 +715,6 @@ lp_emit_instruction_aos(
case TGSI_OPCODE_PK4UB:
return FALSE;
case TGSI_OPCODE_RFL:
return FALSE;
case TGSI_OPCODE_SEQ:
src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
src1 = lp_build_emit_fetch(&bld->bld_base, inst, 1, LP_CHAN_ALL);

56
src/gallium/auxiliary/tgsi/tgsi_exec.c
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@@ -2783,58 +2783,6 @@ exec_scs(struct tgsi_exec_machine *mach,
}
}
static void
exec_rfl(struct tgsi_exec_machine *mach,
const struct tgsi_full_instruction *inst)
{
union tgsi_exec_channel r[9];
if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
/* r0 = dp3(src0, src0) */
fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
micro_mul(&r[0], &r[2], &r[2]);
fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
micro_mul(&r[8], &r[4], &r[4]);
micro_add(&r[0], &r[0], &r[8]);
fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
micro_mul(&r[8], &r[6], &r[6]);
micro_add(&r[0], &r[0], &r[8]);
/* r1 = dp3(src0, src1) */
fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
micro_mul(&r[1], &r[2], &r[3]);
fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
micro_mul(&r[8], &r[4], &r[5]);
micro_add(&r[1], &r[1], &r[8]);
fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
micro_mul(&r[8], &r[6], &r[7]);
micro_add(&r[1], &r[1], &r[8]);
/* r1 = 2 * r1 / r0 */
micro_add(&r[1], &r[1], &r[1]);
micro_div(&r[1], &r[1], &r[0]);
if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
micro_mul(&r[2], &r[2], &r[1]);
micro_sub(&r[2], &r[2], &r[3]);
store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
}
if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
micro_mul(&r[4], &r[4], &r[1]);
micro_sub(&r[4], &r[4], &r[5]);
store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
}
if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
micro_mul(&r[6], &r[6], &r[1]);
micro_sub(&r[6], &r[6], &r[7]);
store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
}
}
if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
}
}
static void
exec_xpd(struct tgsi_exec_machine *mach,
const struct tgsi_full_instruction *inst)
@@ -3782,10 +3730,6 @@ exec_instruction(
assert (0);
break;
case TGSI_OPCODE_RFL:
exec_rfl(mach, inst);
break;
case TGSI_OPCODE_SEQ:
exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;

2
src/gallium/auxiliary/tgsi/tgsi_info.c
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@@ -81,7 +81,7 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 0, 0, 0, 0, COMP, "PK2US", TGSI_OPCODE_PK2US },
{ 1, 1, 0, 0, 0, 0, COMP, "PK4B", TGSI_OPCODE_PK4B },
{ 1, 1, 0, 0, 0, 0, COMP, "PK4UB", TGSI_OPCODE_PK4UB },
{ 1, 2, 0, 0, 0, 0, COMP, "RFL", TGSI_OPCODE_RFL },
{ 0, 1, 0, 0, 0, 1, NONE, "", 44 }, /* removed */
{ 1, 2, 0, 0, 0, 0, COMP, "SEQ", TGSI_OPCODE_SEQ },
{ 1, 2, 0, 0, 0, 0, REPL, "SFL", TGSI_OPCODE_SFL },
{ 1, 2, 0, 0, 0, 0, COMP, "SGT", TGSI_OPCODE_SGT },

1
src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
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@@ -96,7 +96,6 @@ OP11(PK2H)
OP11(PK2US)
OP11(PK4B)
OP11(PK4UB)
OP12(RFL)
OP12(SEQ)
OP12(SFL)
OP12(SGT)

17
src/gallium/docs/source/tgsi.rst
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@@ -476,23 +476,6 @@ while DDY is allowed to be the same for the entire 2x2 quad.
TBD
.. opcode:: RFL - Reflection Vector
.. math::
dst.x = 2 \times (src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z) / (src0.x \times src0.x + src0.y \times src0.y + src0.z \times src0.z) \times src0.x - src1.x
dst.y = 2 \times (src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z) / (src0.x \times src0.x + src0.y \times src0.y + src0.z \times src0.z) \times src0.y - src1.y
dst.z = 2 \times (src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z) / (src0.x \times src0.x + src0.y \times src0.y + src0.z \times src0.z) \times src0.z - src1.z
dst.w = 1
.. note::
Considered for removal.
.. opcode:: SEQ - Set On Equal
.. math::

2
src/gallium/drivers/ilo/shader/toy_tgsi.c
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@@ -838,7 +838,6 @@ static const toy_tgsi_translate aos_translate_table[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_PK2US] = aos_unsupported,
[TGSI_OPCODE_PK4B] = aos_unsupported,
[TGSI_OPCODE_PK4UB] = aos_unsupported,
[TGSI_OPCODE_RFL] = aos_unsupported,
[TGSI_OPCODE_SEQ] = aos_set_on_cond,
[TGSI_OPCODE_SFL] = aos_SFL,
[TGSI_OPCODE_SGT] = aos_set_on_cond,
@@ -1386,7 +1385,6 @@ static const toy_tgsi_translate soa_translate_table[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_PK2US] = soa_unsupported,
[TGSI_OPCODE_PK4B] = soa_unsupported,
[TGSI_OPCODE_PK4UB] = soa_unsupported,
[TGSI_OPCODE_RFL] = soa_unsupported,
[TGSI_OPCODE_SEQ] = soa_per_channel,
[TGSI_OPCODE_SFL] = soa_per_channel,
[TGSI_OPCODE_SGT] = soa_per_channel,

13
src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
View File

@@ -684,19 +684,6 @@ nvfx_fragprog_parse_instruction(struct nvfx_fpc *fpc,
case TGSI_OPCODE_RCP:
nvfx_fp_emit(fpc, arith(sat, RCP, dst, mask, src[0], none, none));
break;
case TGSI_OPCODE_RFL:
if(!fpc->is_nv4x)
nvfx_fp_emit(fpc, arith(0, RFL_NV30, dst, mask, src[0], src[1], none));
else {
tmp = nvfx_src(temp(fpc));
nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[0], none));
nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_Y, src[0], src[1], none));
insn = arith(0, DIV, tmp.reg, NVFX_FP_MASK_Z, swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
insn.scale = NVFX_FP_OP_DST_SCALE_2X;
nvfx_fp_emit(fpc, insn);
nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, swz(tmp, Z, Z, Z, Z), src[0], neg(src[1])));
}
break;
case TGSI_OPCODE_RSQ:
if(!fpc->is_nv4x)
nvfx_fp_emit(fpc, arith(sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none));

1
src/gallium/drivers/r300/r300_tgsi_to_rc.c
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@@ -71,7 +71,6 @@ static unsigned translate_opcode(unsigned opcode)
/* case TGSI_OPCODE_PK2US: return RC_OPCODE_PK2US; */
/* case TGSI_OPCODE_PK4B: return RC_OPCODE_PK4B; */
/* case TGSI_OPCODE_PK4UB: return RC_OPCODE_PK4UB; */
/* case TGSI_OPCODE_RFL: return RC_OPCODE_RFL; */
case TGSI_OPCODE_SEQ: return RC_OPCODE_SEQ;
case TGSI_OPCODE_SFL: return RC_OPCODE_SFL;
case TGSI_OPCODE_SGT: return RC_OPCODE_SGT;

6
src/gallium/drivers/r600/r600_shader.c
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@@ -7232,7 +7232,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
{TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
{44, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
{TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
@@ -7431,7 +7431,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
{TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
{44, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
{TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
@@ -7630,7 +7630,7 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
{TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
{44, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
{TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},

2
src/gallium/include/pipe/p_shader_tokens.h
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@@ -327,7 +327,7 @@ struct tgsi_property_data {
#define TGSI_OPCODE_PK2US 41
#define TGSI_OPCODE_PK4B 42
#define TGSI_OPCODE_PK4UB 43
#define TGSI_OPCODE_RFL 44
/* gap */
#define TGSI_OPCODE_SEQ 45
#define TGSI_OPCODE_SFL 46
#define TGSI_OPCODE_SGT 47