radeonsi: implement PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@@ -488,13 +488,12 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_QUERY_SO_OVERFLOW:
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case PIPE_CAP_MEMOBJ:
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case PIPE_CAP_LOAD_CONSTBUF:
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return 1;
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case PIPE_CAP_INT64:
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case PIPE_CAP_INT64_DIVMOD:
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case PIPE_CAP_TGSI_CLOCK:
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case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
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return 1;
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case PIPE_CAP_TGSI_VOTE:
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@@ -577,7 +576,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_UMA:
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case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
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case PIPE_CAP_POST_DEPTH_COVERAGE:
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case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
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return 0;
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case PIPE_CAP_QUERY_BUFFER_OBJECT:
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@@ -712,8 +712,25 @@ LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
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struct gallivm_state *gallivm = &ctx->gallivm;
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LLVMValueRef result;
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if (ind->File == TGSI_FILE_ADDRESS) {
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result = ctx->addrs[ind->Index][ind->Swizzle];
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result = LLVMBuildLoad(gallivm->builder, result, "");
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} else {
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struct tgsi_full_src_register src = {};
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src.Register.File = ind->File;
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src.Register.Index = ind->Index;
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/* Set the second index to 0 for constants. */
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if (ind->File == TGSI_FILE_CONSTANT)
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src.Register.Dimension = 1;
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result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
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TGSI_TYPE_SIGNED,
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ind->Swizzle);
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result = ac_to_integer(&ctx->ac, result);
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}
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if (addr_mul != 1)
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result = LLVMBuildMul(gallivm->builder, result,
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