radeonsi: implement PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2017-09-26 15:58:13 +02:00
parent 44993bd26f
commit dbe16d7537
2 changed files with 20 additions and 5 deletions

View File

@@ -488,13 +488,12 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_MEMOBJ:
case PIPE_CAP_LOAD_CONSTBUF:
return 1;
case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
case PIPE_CAP_TGSI_CLOCK:
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
return 1;
case PIPE_CAP_TGSI_VOTE:
@@ -577,7 +576,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_UMA:
case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
case PIPE_CAP_POST_DEPTH_COVERAGE:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
return 0;
case PIPE_CAP_QUERY_BUFFER_OBJECT:

View File

@@ -712,8 +712,25 @@ LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
struct gallivm_state *gallivm = &ctx->gallivm;
LLVMValueRef result;
if (ind->File == TGSI_FILE_ADDRESS) {
result = ctx->addrs[ind->Index][ind->Swizzle];
result = LLVMBuildLoad(gallivm->builder, result, "");
} else {
struct tgsi_full_src_register src = {};
src.Register.File = ind->File;
src.Register.Index = ind->Index;
/* Set the second index to 0 for constants. */
if (ind->File == TGSI_FILE_CONSTANT)
src.Register.Dimension = 1;
result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
TGSI_TYPE_SIGNED,
ind->Swizzle);
result = ac_to_integer(&ctx->ac, result);
}
if (addr_mul != 1)
result = LLVMBuildMul(gallivm->builder, result,