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nir: spirv: Allow 32-bit version of nir_intrinsic_is_sparse_texels_resident

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This intrinsic returns a Boolean.  Both 1-bit and 32-bit versions must
be allowed.  Otherwise, size mismatches will occur after lowering
1-bit Booleans to 32-bit.

Fixes: 4cbdf9ec4d ("nir,spirv: implement SpvOpImageSparseTexelsResident")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16547>
This commit is contained in:
Ian Romanick
2022-05-16 18:37:17 -07:00
committed by Marge Bot
parent f73862d339
commit dbd022f2ab
2 changed files with 2 additions and 2 deletions
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2
src/compiler/nir/nir_intrinsics.py
View File

@@ -319,7 +319,7 @@ intrinsic("deref_mode_is", src_comp=[-1], dest_comp=1,
intrinsic("addr_mode_is", src_comp=[-1], dest_comp=1,
indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER])
intrinsic("is_sparse_texels_resident", dest_comp=1, src_comp=[1], bit_sizes=[1],
intrinsic("is_sparse_texels_resident", dest_comp=1, src_comp=[1], bit_sizes=[1,32],
flags=[CAN_ELIMINATE, CAN_REORDER])
# result code is resident only if both inputs are resident
intrinsic("sparse_residency_code_and", dest_comp=1, src_comp=[1, 1], bit_sizes=[32],

2
src/compiler/spirv/spirv_to_nir.c
View File

@@ -2701,7 +2701,7 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp opcode,
return;
} else if (opcode == SpvOpImageSparseTexelsResident) {
nir_ssa_def *code = vtn_get_nir_ssa(b, w[3]);
vtn_push_nir_ssa(b, w[2], nir_is_sparse_texels_resident(&b->nb, code));
vtn_push_nir_ssa(b, w[2], nir_is_sparse_texels_resident(&b->nb, 1, code));
return;
}