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intel/perf: move registers to their own header

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Will conflict with the genxml RPSTAT register.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
This commit is contained in:
Lionel Landwerlin
2019-10-11 15:54:57 +03:00
parent e1d5d75257
commit db7a6847dd
6 changed files with 58 additions and 26 deletions
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1
src/gallium/drivers/iris/iris_monitor.c
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@@ -28,6 +28,7 @@
#include "iris_context.h"
#include "perf/gen_perf.h"
#include "perf/gen_perf_regs.h"
struct iris_monitor_object {
int num_active_counters;

1
src/intel/perf/gen_perf.c
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@@ -33,6 +33,7 @@
#include "common/gen_gem.h"
#include "gen_perf.h"
#include "gen_perf_regs.h"
#include "perf/gen_perf_mdapi.h"
#include "perf/gen_perf_metrics.h"

25
src/intel/perf/gen_perf.h
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@@ -43,18 +43,6 @@ struct gen_device_info;
struct gen_perf_config;
struct gen_perf_query_info;
#define GEN7_RPSTAT1 0xA01C
#define GEN7_RPSTAT1_CURR_GT_FREQ_SHIFT 7
#define GEN7_RPSTAT1_CURR_GT_FREQ_MASK INTEL_MASK(13, 7)
#define GEN7_RPSTAT1_PREV_GT_FREQ_SHIFT 0
#define GEN7_RPSTAT1_PREV_GT_FREQ_MASK INTEL_MASK(6, 0)
#define GEN9_RPSTAT0 0xA01C
#define GEN9_RPSTAT0_CURR_GT_FREQ_SHIFT 23
#define GEN9_RPSTAT0_CURR_GT_FREQ_MASK INTEL_MASK(31, 23)
#define GEN9_RPSTAT0_PREV_GT_FREQ_SHIFT 0
#define GEN9_RPSTAT0_PREV_GT_FREQ_MASK INTEL_MASK(8, 0)
enum gen_perf_counter_type {
GEN_PERF_COUNTER_TYPE_EVENT,
GEN_PERF_COUNTER_TYPE_DURATION_NORM,
@@ -87,19 +75,6 @@ struct gen_pipeline_stat {
*/
#define MAX_OA_REPORT_COUNTERS 62
#define IA_VERTICES_COUNT 0x2310
#define IA_PRIMITIVES_COUNT 0x2318
#define VS_INVOCATION_COUNT 0x2320
#define HS_INVOCATION_COUNT 0x2300
#define DS_INVOCATION_COUNT 0x2308
#define GS_INVOCATION_COUNT 0x2328
#define GS_PRIMITIVES_COUNT 0x2330
#define CL_INVOCATION_COUNT 0x2338
#define CL_PRIMITIVES_COUNT 0x2340
#define PS_INVOCATION_COUNT 0x2348
#define CS_INVOCATION_COUNT 0x2290
#define PS_DEPTH_COUNT 0x2350
/*
* When currently allocate only one page for pipeline statistics queries. Here
* we derived the maximum number of counters for that amount.

54
src/intel/perf/gen_perf_regs.h Normal file
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@@ -0,0 +1,54 @@
/*
* Copyright © 2019 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef GEN_PERF_REGS_H
#define GEN_PERF_REGS_H
/* GT core frequency counters */
#define GEN7_RPSTAT1 0xA01C
#define GEN7_RPSTAT1_CURR_GT_FREQ_SHIFT 7
#define GEN7_RPSTAT1_CURR_GT_FREQ_MASK INTEL_MASK(13, 7)
#define GEN7_RPSTAT1_PREV_GT_FREQ_SHIFT 0
#define GEN7_RPSTAT1_PREV_GT_FREQ_MASK INTEL_MASK(6, 0)
#define GEN9_RPSTAT0 0xA01C
#define GEN9_RPSTAT0_CURR_GT_FREQ_SHIFT 23
#define GEN9_RPSTAT0_CURR_GT_FREQ_MASK INTEL_MASK(31, 23)
#define GEN9_RPSTAT0_PREV_GT_FREQ_SHIFT 0
#define GEN9_RPSTAT0_PREV_GT_FREQ_MASK INTEL_MASK(8, 0)
/* Pipeline statistic counters */
#define IA_VERTICES_COUNT 0x2310
#define IA_PRIMITIVES_COUNT 0x2318
#define VS_INVOCATION_COUNT 0x2320
#define HS_INVOCATION_COUNT 0x2300
#define DS_INVOCATION_COUNT 0x2308
#define GS_INVOCATION_COUNT 0x2328
#define GS_PRIMITIVES_COUNT 0x2330
#define CL_INVOCATION_COUNT 0x2338
#define CL_PRIMITIVES_COUNT 0x2340
#define PS_INVOCATION_COUNT 0x2348
#define CS_INVOCATION_COUNT 0x2290
#define PS_DEPTH_COUNT 0x2350
#endif /* GEN_PERF_REGS_H */

1
src/mesa/drivers/dri/i965/brw_performance_query.c
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@@ -73,6 +73,7 @@
#include "intel_batchbuffer.h"
#include "perf/gen_perf.h"
#include "perf/gen_perf_regs.h"
#include "perf/gen_perf_mdapi.h"
#define FILE_DEBUG_FLAG DEBUG_PERFMON

2
src/mesa/drivers/dri/i965/gen6_queryobj.c
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@@ -36,7 +36,7 @@
#include "brw_context.h"
#include "brw_defines.h"
#include "brw_state.h"
#include "perf/gen_perf.h"
#include "perf/gen_perf_regs.h"
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"