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intel/blorp: Use WA helpers for depth pipecontrol

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Instead of unconditionally emitting a pipe control on gfx11+, use the
workaround helpers for workarounds 1408224581 and 14014097488. Also, add
a check for workaround 14016712196, which is also impacted.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29922>
This commit is contained in:
Nanley Chery
2024-07-02 11:02:04 -04:00
committed by Marge Bot
parent 77e4f9690d
commit db6ae41c65
1 changed files with 19 additions and 14 deletions
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33
src/intel/blorp/blorp_genX_exec_brw.h
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@@ -1307,6 +1307,8 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
const struct blorp_params *params) const struct blorp_params *params)
{ {
const struct isl_device *isl_dev = batch->blorp->isl_dev; const struct isl_device *isl_dev = batch->blorp->isl_dev;
const struct intel_device_info *devinfo =
batch->blorp->compiler->brw->devinfo;
uint32_t *dw = blorp_emit_dwords(batch, isl_dev->ds.size / 4); uint32_t *dw = blorp_emit_dwords(batch, isl_dev->ds.size / 4);
if (dw == NULL) if (dw == NULL)
@@ -1358,21 +1360,24 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info); isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info);
#if GFX_VER >= 11 if (intel_needs_workaround(devinfo, 1408224581) ||
/* Wa_1408224581 intel_needs_workaround(devinfo, 14014097488) ||
* intel_needs_workaround(devinfo, 14016712196)) {
* Workaround: Gfx12LP Astep only An additional pipe control with /* Wa_1408224581
* post-sync = store dword operation would be required.( w/a is to *
* have an additional pipe control after the stencil state whenever * Workaround: Gfx12LP Astep only An additional pipe control with
* the surface state bits of this state is changing). * post-sync = store dword operation would be required.( w/a is to
* * have an additional pipe control after the stencil state whenever
* This also seems sufficient to handle Wa_14014097488. * the surface state bits of this state is changing).
*/ *
blorp_emit(batch, GENX(PIPE_CONTROL), pc) { * This also seems sufficient to handle Wa_14014097488 and
pc.PostSyncOperation = WriteImmediateData; * Wa_14016712196.
pc.Address = blorp_get_workaround_address(batch); */
blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
pc.PostSyncOperation = WriteImmediateData;
pc.Address = blorp_get_workaround_address(batch);
}
} }
#endif
} }
/* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The