From db41d62be99655893f5b54794326cd5c7cbfd79e Mon Sep 17 00:00:00 2001 From: Mike Blumenkrantz Date: Mon, 17 Oct 2022 11:49:05 -0400 Subject: [PATCH] zink: use Aligned with global load/store ops this is required by spec Fixes: ddc5c304899 ("zink: handle global and scratch vars") Part-of: --- .../drivers/zink/nir_to_spirv/nir_to_spirv.c | 4 ++-- .../drivers/zink/nir_to_spirv/spirv_builder.c | 17 +++++++++++++++++ .../drivers/zink/nir_to_spirv/spirv_builder.h | 4 ++++ 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index c810d047208..f7121913e08 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -2502,7 +2502,7 @@ emit_load_global(struct ntv_context *ctx, nir_intrinsic_instr *intr) dest_type); nir_alu_type atype; SpvId ptr = emit_bitcast(ctx, pointer_type, get_src(ctx, &intr->src[0], &atype)); - SpvId result = spirv_builder_emit_load(&ctx->builder, dest_type, ptr); + SpvId result = spirv_builder_emit_load_aligned(&ctx->builder, dest_type, ptr, intr->def.bit_size / 8); store_def(ctx, &intr->def, result, nir_type_uint); } @@ -2518,7 +2518,7 @@ emit_store_global(struct ntv_context *ctx, nir_intrinsic_instr *intr) nir_alu_type atype; SpvId param = get_src(ctx, &intr->src[0], &atype); SpvId ptr = emit_bitcast(ctx, pointer_type, get_src(ctx, &intr->src[1], &atype)); - spirv_builder_emit_store(&ctx->builder, ptr, param); + spirv_builder_emit_store_aligned(&ctx->builder, ptr, param, bit_size / 8); } static void diff --git a/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.c b/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.c index 8bc477d777e..768b31f9389 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.c +++ b/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.c @@ -469,6 +469,12 @@ spirv_builder_emit_load(struct spirv_builder *b, SpvId result_type, return spirv_builder_emit_unop(b, SpvOpLoad, result_type, pointer); } +SpvId +spirv_builder_emit_load_aligned(struct spirv_builder *b, SpvId result_type, SpvId pointer, unsigned alignment) +{ + return spirv_builder_emit_triop(b, SpvOpLoad, result_type, pointer, SpvMemoryAccessAlignedMask, alignment); +} + void spirv_builder_emit_store(struct spirv_builder *b, SpvId pointer, SpvId object) { @@ -478,6 +484,17 @@ spirv_builder_emit_store(struct spirv_builder *b, SpvId pointer, SpvId object) spirv_buffer_emit_word(&b->instructions, object); } +void +spirv_builder_emit_store_aligned(struct spirv_builder *b, SpvId pointer, SpvId object, unsigned alignment) +{ + spirv_buffer_prepare(&b->instructions, b->mem_ctx, 5); + spirv_buffer_emit_word(&b->instructions, SpvOpStore | (5 << 16)); + spirv_buffer_emit_word(&b->instructions, pointer); + spirv_buffer_emit_word(&b->instructions, object); + spirv_buffer_emit_word(&b->instructions, SpvMemoryAccessAlignedMask); + spirv_buffer_emit_word(&b->instructions, alignment); +} + void spirv_builder_emit_atomic_store(struct spirv_builder *b, SpvId pointer, SpvScope scope, SpvMemorySemanticsMask semantics, SpvId object) diff --git a/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.h b/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.h index a3d2a4f0c38..dabf6f71440 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.h +++ b/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.h @@ -187,12 +187,16 @@ SpvId spirv_builder_emit_load(struct spirv_builder *b, SpvId result_type, SpvId pointer); +SpvId +spirv_builder_emit_load_aligned(struct spirv_builder *b, SpvId result_type, SpvId pointer, unsigned alignment); void spirv_builder_emit_atomic_store(struct spirv_builder *b, SpvId pointer, SpvScope scope, SpvMemorySemanticsMask semantics, SpvId object); void spirv_builder_emit_store(struct spirv_builder *b, SpvId pointer, SpvId object); +void +spirv_builder_emit_store_aligned(struct spirv_builder *b, SpvId pointer, SpvId object, unsigned alignment); SpvId spirv_builder_emit_access_chain(struct spirv_builder *b, SpvId result_type,