radv: change use_aco -> use_llvm

We are about to make ACO the default backend.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5445>

src/amd/vulkan/radv_cmd_buffer.c

@@ -2953,7 +2953,7 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
 			flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
 			/* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
 			 * invalidate the scalar cache. */
-			if (cmd_buffer->device->physical_device->use_aco)
+			if (!cmd_buffer->device->physical_device->use_llvm)
 				flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
 
 			if (!image_is_coherent)

src/amd/vulkan/radv_debug.c

@@ -433,7 +433,7 @@ radv_dump_shader(struct radv_pipeline *pipeline,
 	}
 
 	fprintf(f, "%s IR:\n%s\n",
-		pipeline->device->physical_device->use_aco ? "ACO" : "LLVM",
+		pipeline->device->physical_device->use_llvm ? "LLVM" : "ACO",
 		shader->ir_string);
 	fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
 

src/amd/vulkan/radv_device.c

@@ -230,7 +230,7 @@ radv_physical_device_init_mem_types(struct radv_physical_device *device)
 static const char *
 radv_get_compiler_string(struct radv_physical_device *pdevice)
 {
-	if (pdevice->use_aco) {
+	if (!pdevice->use_llvm) {
 		/* Some games like SotTR apply shader workarounds if the LLVM
 		 * version is too old or if the LLVM version string is
 		 * missing. This gives 2-5% performance with SotTR and ACO.
@@ -338,7 +338,7 @@ radv_physical_device_try_create(struct radv_instance *instance,
 	device->local_fd = fd;
 	device->ws->query_info(device->ws, &device->rad_info);
 
-	device->use_aco = instance->perftest_flags & RADV_PERFTEST_ACO;
+	device->use_llvm = !(instance->perftest_flags & RADV_PERFTEST_ACO);
 
 	snprintf(device->name, sizeof(device->name),
 		 "AMD RADV %s (%s)",
@@ -351,7 +351,7 @@ radv_physical_device_try_create(struct radv_instance *instance,
 	}
 
 	/* These flags affect shader compilation. */
-	uint64_t shader_env_flags = (device->use_aco ? 0x2 : 0);
+	uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
 
 	/* The gpu id is already embedded in the uuid so we just pass "radv"
 	 * when creating the cache.
@@ -372,7 +372,7 @@ radv_physical_device_try_create(struct radv_instance *instance,
 	device->dcc_msaa_allowed =
 		(device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
 
-	device->use_shader_ballot = (device->use_aco && device->rad_info.chip_class >= GFX8) ||
+	device->use_shader_ballot = (!device->use_llvm && device->rad_info.chip_class >= GFX8) ||
 				    (device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT);
 
 	device->use_ngg = device->rad_info.chip_class >= GFX10 &&
@@ -380,7 +380,7 @@ radv_physical_device_try_create(struct radv_instance *instance,
 			  !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
 
 	/* TODO: Implement NGG GS with ACO. */
-	device->use_ngg_gs = device->use_ngg && !device->use_aco;
+	device->use_ngg_gs = device->use_ngg && device->use_llvm;
 	device->use_ngg_streamout = false;
 
 	/* Determine the number of threads per wave for all stages. */
@@ -976,7 +976,7 @@ radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
 	f->storageBuffer16BitAccess            = true;
 	f->uniformAndStorageBuffer16BitAccess  = true;
 	f->storagePushConstant16               = true;
-	f->storageInputOutput16                = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || pdevice->use_aco);
+	f->storageInputOutput16                = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
 	f->multiview                           = true;
 	f->multiviewGeometryShader             = true;
 	f->multiviewTessellationShader         = true;
@@ -998,8 +998,8 @@ radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
 	f->storageBuffer8BitAccess = true;
 	f->uniformAndStorageBuffer8BitAccess = true;
 	f->storagePushConstant8 = true;
-	f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || pdevice->use_aco;
-	f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || pdevice->use_aco;
+	f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
+	f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
 	f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
 	f->shaderInt8 = true;
 
@@ -1217,7 +1217,7 @@ void radv_GetPhysicalDeviceFeatures2(
 		case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
 			VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
 				(VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
-			features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || pdevice->use_aco;
+			features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
 			break;
 		}
 		case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {

src/amd/vulkan/radv_extensions.py

@@ -94,7 +94,7 @@ EXTENSIONS = [
     Extension('VK_KHR_sampler_mirror_clamp_to_edge',      1, True),
     Extension('VK_KHR_sampler_ycbcr_conversion',          1, True),
     Extension('VK_KHR_separate_depth_stencil_layouts',    1, True),
-    Extension('VK_KHR_shader_atomic_int64',               1, 'LLVM_VERSION_MAJOR >= 9 || device->use_aco'),
+    Extension('VK_KHR_shader_atomic_int64',               1, 'LLVM_VERSION_MAJOR >= 9 || !device->use_llvm'),
     Extension('VK_KHR_shader_clock',                      1, True),
     Extension('VK_KHR_shader_draw_parameters',            1, True),
     Extension('VK_KHR_shader_float_controls',             1, True),
@@ -151,7 +151,7 @@ EXTENSIONS = [
     Extension('VK_EXT_sample_locations',                  1, 'device->rad_info.chip_class < GFX10'),
     Extension('VK_EXT_sampler_filter_minmax',             1, True),
     Extension('VK_EXT_scalar_block_layout',               1, 'device->rad_info.chip_class >= GFX7'),
-    Extension('VK_EXT_shader_demote_to_helper_invocation',1, 'LLVM_VERSION_MAJOR >= 9 || device->use_aco'),
+    Extension('VK_EXT_shader_demote_to_helper_invocation',1, 'LLVM_VERSION_MAJOR >= 9 || !device->use_llvm'),
     Extension('VK_EXT_shader_viewport_index_layer',       1, True),
     Extension('VK_EXT_shader_stencil_export',             1, True),
     Extension('VK_EXT_shader_subgroup_ballot',            1, True),

src/amd/vulkan/radv_pipeline.c

@@ -222,8 +222,8 @@ static uint32_t get_hash_flags(struct radv_device *device)
 		hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
 	if (device->physical_device->ge_wave_size == 32)
 		hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
-	if (device->physical_device->use_aco)
-		hash_flags |= RADV_HASH_SHADER_ACO;
+	if (device->physical_device->use_llvm)
+		hash_flags |= RADV_HASH_SHADER_LLVM;
 	return hash_flags;
 }
 
@@ -2521,7 +2521,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
 					  pipeline->layout,
 					  &keys[MESA_SHADER_FRAGMENT],
 					  &infos[MESA_SHADER_FRAGMENT],
-					  pipeline->device->physical_device->use_aco);
+					  pipeline->device->physical_device->use_llvm);
 
 		/* TODO: These are no longer used as keys we should refactor this */
 		keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
@@ -2573,7 +2573,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
 			radv_nir_shader_info_pass(combined_nir[i],
 						  pipeline->layout, &key,
 						  &infos[MESA_SHADER_TESS_CTRL],
-						  pipeline->device->physical_device->use_aco);
+						  pipeline->device->physical_device->use_llvm);
 		}
 
 		keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
@@ -2597,7 +2597,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
 						  pipeline->layout,
 						  &keys[pre_stage],
 						  &infos[MESA_SHADER_GEOMETRY],
-						  pipeline->device->physical_device->use_aco);
+						  pipeline->device->physical_device->use_llvm);
 		}
 
 		filled_stages |= (1 << pre_stage);
@@ -2622,7 +2622,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
 
 		radv_nir_shader_info_init(&infos[i]);
 		radv_nir_shader_info_pass(nir[i], pipeline->layout,
-					  &keys[i], &infos[i], pipeline->device->physical_device->use_aco);
+					  &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
 	}
 
 	for (int i = 0; i < MESA_SHADER_STAGES; i++) {
@@ -2832,14 +2832,15 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
 			/* do this again since information such as outputs_read can be out-of-date */
 			nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
 
-			if (device->physical_device->use_aco) {
+			if (device->physical_device->use_llvm) {
+				NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
+			} else {
 				NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
 				           nir_lower_non_uniform_ubo_access |
 				           nir_lower_non_uniform_ssbo_access |
 				           nir_lower_non_uniform_texture_access |
 				           nir_lower_non_uniform_image_access);
-			} else
-				NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
+			}
 		}
 	}
 
@@ -2888,7 +2889,7 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
 
 			radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
 						  pipeline->layout, &key,
-						  &info, pipeline->device->physical_device->use_aco);
+						  &info, pipeline->device->physical_device->use_llvm);
 			info.wave_size = 64; /* Wave32 not supported. */
 			info.ballot_bit_size = 64;
 
@@ -5744,12 +5745,12 @@ VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
 	/* backend IR */
 	if (p < end) {
 		p->isText = true;
-		if (pipeline->device->physical_device->use_aco) {
-			desc_copy(p->name, "ACO IR");
-			desc_copy(p->description, "The ACO IR after some optimizations");
-		} else {
+		if (pipeline->device->physical_device->use_llvm) {
 			desc_copy(p->name, "LLVM IR");
 			desc_copy(p->description, "The LLVM IR after some optimizations");
+		} else {
+			desc_copy(p->name, "ACO IR");
+			desc_copy(p->description, "The ACO IR after some optimizations");
 		}
 		if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
 			result = VK_INCOMPLETE;

src/amd/vulkan/radv_private.h

@@ -311,8 +311,8 @@ struct radv_physical_device {
 	uint8_t cs_wave_size;
 	uint8_t ge_wave_size;
 
-	/* Whether to use the experimental compiler backend */
-	bool use_aco;
+	/* Whether to use the LLVM compiler backend */
+	bool use_llvm;
 
 	/* This is the drivers on-disk cache used as a fallback as opposed to
 	 * the pipeline cache defined by apps.
@@ -1581,7 +1581,7 @@ struct radv_shader_module;
 #define RADV_HASH_SHADER_CS_WAVE32           (1 << 1)
 #define RADV_HASH_SHADER_PS_WAVE32           (1 << 2)
 #define RADV_HASH_SHADER_GE_WAVE32           (1 << 3)
-#define RADV_HASH_SHADER_ACO                 (1 << 4)
+#define RADV_HASH_SHADER_LLVM                (1 << 4)
 
 void
 radv_hash_shaders(unsigned char *hash,
@@ -2396,7 +2396,7 @@ void radv_nir_shader_info_pass(const struct nir_shader *nir,
 			       const struct radv_pipeline_layout *layout,
 			       const struct radv_shader_variant_key *key,
 			       struct radv_shader_info *info,
-			       bool use_aco);
+			       bool use_llvm);
 
 void radv_nir_shader_info_init(struct radv_shader_info *info);
 

src/amd/vulkan/radv_shader.c

@@ -309,8 +309,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
 {
 	nir_shader *nir;
 	const nir_shader_compiler_options *nir_options =
-		device->physical_device->use_aco ? &nir_options_aco :
-						   &nir_options_llvm;
+		device->physical_device->use_llvm ? &nir_options_llvm :
+						    &nir_options_aco;
 
 	if (module->nir) {
 		/* Some things such as our meta clear/blit code will give us a NIR
@@ -458,7 +458,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
 		NIR_PASS_V(nir, nir_split_per_member_structs);
 
 		if (nir->info.stage == MESA_SHADER_FRAGMENT &&
-		    device->physical_device->use_aco)
+		    !device->physical_device->use_llvm)
                         NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
 		if (nir->info.stage == MESA_SHADER_FRAGMENT)
 			NIR_PASS_V(nir, nir_lower_input_attachments, true);
@@ -1166,14 +1166,14 @@ shader_variant_compile(struct radv_device *device,
 				 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
 						   : MESA_SHADER_VERTEX);
 
-	if (!device->physical_device->use_aco ||
+	if (device->physical_device->use_llvm ||
 	    options->dump_shader || options->record_ir)
 		ac_init_llvm_once();
 
-	if (device->physical_device->use_aco) {
-		aco_compile_shader(shader_count, shaders, &binary, &args);
-	} else {
+	if (device->physical_device->use_llvm) {
 		llvm_compile_shader(device, shader_count, shaders, &binary, &args);
+	} else {
+		aco_compile_shader(shader_count, shaders, &binary, &args);
 	}
 
 	binary->info = *info;
@@ -1234,7 +1234,7 @@ radv_shader_variant_compile(struct radv_device *device,
 	if (key)
 		options.key = *key;
 
-	options.explicit_scratch_args = device->physical_device->use_aco;
+	options.explicit_scratch_args = !device->physical_device->use_llvm;
 	options.robust_buffer_access = device->robust_buffer_access;
 
 	return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
@@ -1251,7 +1251,7 @@ radv_create_gs_copy_shader(struct radv_device *device,
 {
 	struct radv_nir_compiler_options options = {0};
 
-	options.explicit_scratch_args = device->physical_device->use_aco;
+	options.explicit_scratch_args = !device->physical_device->use_llvm;
 	options.key.has_multiview_view_index = multiview;
 
 	return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,

src/amd/vulkan/radv_shader_info.c

@@ -668,7 +668,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
 			  const struct radv_pipeline_layout *layout,
 			  const struct radv_shader_variant_key *key,
 			  struct radv_shader_info *info,
-			  bool use_aco)
+			  bool use_llvm)
 {
 	struct nir_function *func =
 		(struct nir_function *)exec_list_get_head_const(&nir->functions);
@@ -822,13 +822,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
 		struct radv_es_output_info *es_info =
 			nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
 
-		if (use_aco) {
-			/* The outputs don't contain gaps, se we can use the number of outputs */
-			uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
-				? info->vs.num_linked_outputs
-				: info->tes.num_linked_outputs;
-			es_info->esgs_itemsize = num_outputs_written * 16;
-		} else {
+		if (use_llvm) {
 			/* The outputs may contain gaps, use the highest output index + 1 */
 			uint32_t max_output_written = 0;
 			uint64_t output_mask = nir->info.outputs_written;
@@ -839,8 +833,13 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
 
 				max_output_written = MAX2(param_index, max_output_written);
 			}
-
 			es_info->esgs_itemsize = (max_output_written + 1) * 16;
+		} else {
+			/* The outputs don't contain gaps, se we can use the number of outputs */
+			uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
+				? info->vs.num_linked_outputs
+				: info->tes.num_linked_outputs;
+			es_info->esgs_itemsize = num_outputs_written * 16;
 		}
 	}