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dzn: Implement subgroup size control extension

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20801>
This commit is contained in:
Jesse Natalie
2023-01-19 13:30:49 -08:00
parent a041cd48f4
commit db083070f0
2 changed files with 16 additions and 5 deletions
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9
src/microsoft/vulkan/dzn_device.c
View File

@@ -109,6 +109,7 @@ dzn_physical_device_get_extensions(struct dzn_physical_device *pdev)
#endif #endif
.EXT_shader_subgroup_ballot = true, .EXT_shader_subgroup_ballot = true,
.EXT_shader_subgroup_vote = true, .EXT_shader_subgroup_vote = true,
.EXT_subgroup_size_control = true,
.EXT_vertex_attribute_divisor = true, .EXT_vertex_attribute_divisor = true,
}; };
} }
@@ -1411,8 +1412,8 @@ dzn_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice,
.privateData = true, .privateData = true,
.shaderDemoteToHelperInvocation = false, .shaderDemoteToHelperInvocation = false,
.shaderTerminateInvocation = false, .shaderTerminateInvocation = false,
.subgroupSizeControl = false, .subgroupSizeControl = pdev->options1.WaveOps && pdev->shader_model >= D3D_SHADER_MODEL_6_6,
.computeFullSubgroups = false, .computeFullSubgroups = true,
.synchronization2 = true, .synchronization2 = true,
.textureCompressionASTC_HDR = false, .textureCompressionASTC_HDR = false,
.shaderZeroInitializeWorkgroupMemory = false, .shaderZeroInitializeWorkgroupMemory = false,
@@ -1817,10 +1818,10 @@ dzn_GetPhysicalDeviceProperties2(VkPhysicalDevice physicalDevice,
const VkPhysicalDeviceVulkan13Properties core_1_3 = { const VkPhysicalDeviceVulkan13Properties core_1_3 = {
.sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_3_PROPERTIES, .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_3_PROPERTIES,
.minSubgroupSize = pdevice->options1.WaveOps ? pdevice->options1.WaveLaneCountMin : 1, .minSubgroupSize = pdevice->options1.WaveOps ? pdevice->options1.WaveLaneCountMin : 1,
.minSubgroupSize = pdevice->options1.WaveOps ? pdevice->options1.WaveLaneCountMax : 1, .maxSubgroupSize = pdevice->options1.WaveOps ? pdevice->options1.WaveLaneCountMax : 1,
.maxComputeWorkgroupSubgroups = D3D12_CS_THREAD_GROUP_MAX_THREADS_PER_GROUP / .maxComputeWorkgroupSubgroups = D3D12_CS_THREAD_GROUP_MAX_THREADS_PER_GROUP /
(pdevice->options1.WaveOps ? pdevice->options1.WaveLaneCountMin : 1), (pdevice->options1.WaveOps ? pdevice->options1.WaveLaneCountMin : 1),
.requiredSubgroupSizeStages = 0, .requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT,
}; };
vk_foreach_struct(ext, pProperties->pNext) { vk_foreach_struct(ext, pProperties->pNext) {

12
src/microsoft/vulkan/dzn_pipeline.c
View File

@@ -195,6 +195,7 @@ struct dzn_nir_options {
bool lower_view_index_to_rt_layer; bool lower_view_index_to_rt_layer;
enum pipe_format *vi_conversions; enum pipe_format *vi_conversions;
const nir_shader_compiler_options *nir_opts; const nir_shader_compiler_options *nir_opts;
enum gl_subgroup_size subgroup_size;
}; };
static VkResult static VkResult
@@ -259,6 +260,7 @@ dzn_pipeline_get_nir_shader(struct dzn_device *device,
if (needs_conv) if (needs_conv)
NIR_PASS_V(*nir, dxil_nir_lower_vs_vertex_conversion, options->vi_conversions); NIR_PASS_V(*nir, dxil_nir_lower_vs_vertex_conversion, options->vi_conversions);
} }
(*nir)->info.subgroup_size = options->subgroup_size;
if (cache) if (cache)
vk_pipeline_cache_add_nir(cache, hash, SHA1_DIGEST_LENGTH, *nir); vk_pipeline_cache_add_nir(cache, hash, SHA1_DIGEST_LENGTH, *nir);
@@ -791,6 +793,12 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
struct mesa_sha1 nir_hash_ctx; struct mesa_sha1 nir_hash_ctx;
uint8_t nir_hash[SHA1_DIGEST_LENGTH]; uint8_t nir_hash[SHA1_DIGEST_LENGTH];
const VkPipelineShaderStageRequiredSubgroupSizeCreateInfo *subgroup_size =
(const VkPipelineShaderStageRequiredSubgroupSizeCreateInfo *)
vk_find_struct_const(stages[stage].info->pNext, PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO);
enum gl_subgroup_size subgroup_enum = subgroup_size && subgroup_size->requiredSubgroupSize >= 8 ?
subgroup_size->requiredSubgroupSize : SUBGROUP_SIZE_FULL_SUBGROUPS;
if (cache) { if (cache) {
_mesa_sha1_init(&nir_hash_ctx); _mesa_sha1_init(&nir_hash_ctx);
if (stage != MESA_SHADER_FRAGMENT) if (stage != MESA_SHADER_FRAGMENT)
@@ -803,6 +811,7 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
_mesa_sha1_update(&nir_hash_ctx, &z_flip_mask, sizeof(z_flip_mask)); _mesa_sha1_update(&nir_hash_ctx, &z_flip_mask, sizeof(z_flip_mask));
_mesa_sha1_update(&nir_hash_ctx, &lower_view_index, sizeof(lower_view_index)); _mesa_sha1_update(&nir_hash_ctx, &lower_view_index, sizeof(lower_view_index));
} }
_mesa_sha1_update(&nir_hash_ctx, &subgroup_enum, sizeof(subgroup_enum));
_mesa_sha1_update(&nir_hash_ctx, stages[stage].spirv_hash, sizeof(stages[stage].spirv_hash)); _mesa_sha1_update(&nir_hash_ctx, stages[stage].spirv_hash, sizeof(stages[stage].spirv_hash));
_mesa_sha1_final(&nir_hash_ctx, nir_hash); _mesa_sha1_final(&nir_hash_ctx, nir_hash);
} }
@@ -815,7 +824,8 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
.lower_view_index = lower_view_index, .lower_view_index = lower_view_index,
.lower_view_index_to_rt_layer = stage == last_raster_stage ? lower_view_index : false, .lower_view_index_to_rt_layer = stage == last_raster_stage ? lower_view_index : false,
.vi_conversions = vi_conversions, .vi_conversions = vi_conversions,
.nir_opts = &nir_opts .nir_opts = &nir_opts,
.subgroup_size = subgroup_enum,
}; };
ret = dzn_pipeline_get_nir_shader(device, layout, ret = dzn_pipeline_get_nir_shader(device, layout,