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intel: Add workaround for stencil state.

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Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
This commit is contained in:
Rafael Antognolli
2019-11-13 14:30:57 -08:00
parent d2cf3cad91
commit dadb6ebbd1
3 changed files with 40 additions and 0 deletions
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12
src/gallium/drivers/iris/iris_state.c
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@@ -5612,6 +5612,18 @@ iris_upload_dirty_render_state(struct iris_context *ice,
uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4;
uint32_t cso_z_size = sizeof(cso_z->packets) - clear_length;
iris_batch_emit(batch, cso_z->packets, cso_z_size);
if (GEN_GEN >= 12) {
/* GEN:BUG:1408224581
*
* Workaround: Gen12LP Astep only An additional pipe control with
* post-sync = store dword operation would be required.( w/a is to
* have an additional pipe control after the stencil state whenever
* the surface state bits of this state is changing).
*/
iris_emit_pipe_control_write(batch, "WA for stencil state",
PIPE_CONTROL_WRITE_IMMEDIATE,
batch->screen->workaround_bo, 0, 0);
}
union isl_color_value clear_value = { .f32 = { 0, } };

14
src/intel/blorp/blorp_genX_exec.h
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@@ -1624,6 +1624,20 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
}
isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info);
#if GEN_GEN >= 12
/* GEN:BUG:1408224581
*
* Workaround: Gen12LP Astep only An additional pipe control with
* post-sync = store dword operation would be required.( w/a is to
* have an additional pipe control after the stencil state whenever
* the surface state bits of this state is changing).
*/
blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
pc.PostSyncOperation = WriteImmediateData;
pc.Address = blorp_get_workaround_page(batch);
}
#endif
}
#if GEN_GEN >= 8

14
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -4096,6 +4096,20 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
isl_emit_depth_stencil_hiz_s(&device->isl_dev, dw, &info);
if (GEN_GEN >= 12) {
/* GEN:BUG:1408224581
*
* Workaround: Gen12LP Astep only An additional pipe control with
* post-sync = store dword operation would be required.( w/a is to
* have an additional pipe control after the stencil state whenever
* the surface state bits of this state is changing).
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.PostSyncOperation = WriteImmediateData;
pc.Address =
(struct anv_address) { cmd_buffer->device->workaround_bo, 0 };
}
}
cmd_buffer->state.hiz_enabled = info.hiz_usage == ISL_AUX_USAGE_HIZ;
}