radeonsi: fix initialization of occlusion query buffers for disabled RBs
GFX9+ should assume the enabled RB results are packed (no holes). Same as PAL. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
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@@ -589,20 +589,32 @@ static bool si_query_hw_prepare_buffer(struct si_context *sctx, struct si_query_
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query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
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query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
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unsigned max_rbs = screen->info.max_render_backends;
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uint64_t enabled_rb_mask = screen->info.enabled_rb_mask;
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unsigned num_results;
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unsigned i, j;
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unsigned num_results = qbuf->buf->b.b.width0 / query->result_size;
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/* Set top bits for unused backends. */
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num_results = qbuf->buf->b.b.width0 / query->result_size;
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for (j = 0; j < num_results; j++) {
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for (i = 0; i < max_rbs; i++) {
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if (!(enabled_rb_mask & (1ull << i))) {
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if (screen->info.gfx_level >= GFX9) {
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unsigned num_rbs = screen->info.num_rb;
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for (unsigned j = 0; j < num_results; j++) {
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/* Results of enabled RBs are packed, so the disabled ones are always at the end. */
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for (unsigned i = num_rbs; i < max_rbs; i++) {
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results[(i * 4) + 1] = 0x80000000;
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results[(i * 4) + 3] = 0x80000000;
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}
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results += 4 * max_rbs;
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}
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} else {
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uint64_t enabled_rb_mask = screen->info.enabled_rb_mask;
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/* Set top bits for unused backends. */
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for (unsigned j = 0; j < num_results; j++) {
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for (unsigned i = 0; i < max_rbs; i++) {
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if (!(enabled_rb_mask & (1ull << i))) {
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results[(i * 4) + 1] = 0x80000000;
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results[(i * 4) + 3] = 0x80000000;
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}
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}
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results += 4 * max_rbs;
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}
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results += 4 * max_rbs;
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}
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}
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