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radv: configure VGT_TF_PARAM directly from the command buffer

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The driver re-emits the tessellation domain origin state when a new
pipeline with tessellation is bound, so this can be moved there.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20486>
This commit is contained in:
Samuel Pitoiset
2023-01-09 12:57:07 +01:00
committed by Marge Bot
parent f1b3e6aefd
commit d944959fbf
3 changed files with 43 additions and 60 deletions
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50
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1928,9 +1928,6 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP |
RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP_ENABLE;
if (cmd_buffer->state.emitted_graphics_pipeline->vgt_tf_param != pipeline->vgt_tf_param)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_TESS_DOMAIN_ORIGIN;
if (memcmp(cmd_buffer->state.emitted_graphics_pipeline->cb_blend_control,
pipeline->cb_blend_control, sizeof(pipeline->cb_blend_control)) ||
memcmp(cmd_buffer->state.emitted_graphics_pipeline->sx_mrt_blend_opt,
@@ -3949,12 +3946,50 @@ radv_emit_vertex_input(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirt
static void
radv_emit_tess_domain_origin(struct radv_cmd_buffer *cmd_buffer)
{
const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device;
const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
const struct radv_shader *tes = radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL);
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
unsigned vgt_tf_param = pipeline->vgt_tf_param;
unsigned type = 0, partitioning = 0, distribution_mode = 0;
unsigned topology;
switch (tes->info.tes._primitive_mode) {
case TESS_PRIMITIVE_TRIANGLES:
type = V_028B6C_TESS_TRIANGLE;
break;
case TESS_PRIMITIVE_QUADS:
type = V_028B6C_TESS_QUAD;
break;
case TESS_PRIMITIVE_ISOLINES:
type = V_028B6C_TESS_ISOLINE;
break;
default:
unreachable("Invalid tess primitive type");
}
switch (tes->info.tes.spacing) {
case TESS_SPACING_EQUAL:
partitioning = V_028B6C_PART_INTEGER;
break;
case TESS_SPACING_FRACTIONAL_ODD:
partitioning = V_028B6C_PART_FRAC_ODD;
break;
case TESS_SPACING_FRACTIONAL_EVEN:
partitioning = V_028B6C_PART_FRAC_EVEN;
break;
default:
unreachable("Invalid tess spacing type");
}
if (pdevice->rad_info.has_distributed_tess) {
if (pdevice->rad_info.family == CHIP_FIJI || pdevice->rad_info.family >= CHIP_POLARIS10)
distribution_mode = V_028B6C_TRAPEZOIDS;
else
distribution_mode = V_028B6C_DONUTS;
} else {
distribution_mode = V_028B6C_NO_DIST;
}
if (tes->info.tes.point_mode) {
topology = V_028B6C_OUTPUT_POINT;
} else if (tes->info.tes._primitive_mode == TESS_PRIMITIVE_ISOLINES) {
@@ -3969,9 +4004,10 @@ radv_emit_tess_domain_origin(struct radv_cmd_buffer *cmd_buffer)
topology = ccw ? V_028B6C_OUTPUT_TRIANGLE_CCW : V_028B6C_OUTPUT_TRIANGLE_CW;
}
vgt_tf_param |= S_028B6C_TOPOLOGY(topology);
radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM, vgt_tf_param);
radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
S_028B6C_TOPOLOGY(topology) |
S_028B6C_DISTRIBUTION_MODE(distribution_mode));
}
static void

52
src/amd/vulkan/radv_pipeline.c
View File

@@ -5051,54 +5051,6 @@ radv_pipeline_init_vgt_gs_out(struct radv_graphics_pipeline *pipeline,
return gs_out;
}
static void
radv_pipeline_init_tess_state(struct radv_graphics_pipeline *pipeline,
const struct vk_graphics_pipeline_state *state)
{
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
struct radv_shader *tes = radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL);
unsigned type = 0, partitioning = 0, distribution_mode = 0;
switch (tes->info.tes._primitive_mode) {
case TESS_PRIMITIVE_TRIANGLES:
type = V_028B6C_TESS_TRIANGLE;
break;
case TESS_PRIMITIVE_QUADS:
type = V_028B6C_TESS_QUAD;
break;
case TESS_PRIMITIVE_ISOLINES:
type = V_028B6C_TESS_ISOLINE;
break;
default:
break;
}
switch (tes->info.tes.spacing) {
case TESS_SPACING_EQUAL:
partitioning = V_028B6C_PART_INTEGER;
break;
case TESS_SPACING_FRACTIONAL_ODD:
partitioning = V_028B6C_PART_FRAC_ODD;
break;
case TESS_SPACING_FRACTIONAL_EVEN:
partitioning = V_028B6C_PART_FRAC_EVEN;
break;
default:
break;
}
if (pdevice->rad_info.has_distributed_tess) {
if (pdevice->rad_info.family == CHIP_FIJI || pdevice->rad_info.family >= CHIP_POLARIS10)
distribution_mode = V_028B6C_TRAPEZOIDS;
else
distribution_mode = V_028B6C_DONUTS;
} else
distribution_mode = V_028B6C_NO_DIST;
pipeline->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
S_028B6C_DISTRIBUTION_MODE(distribution_mode);
}
static void
radv_pipeline_init_extra(struct radv_graphics_pipeline *pipeline,
const struct radv_graphics_pipeline_create_info *extra,
@@ -5277,10 +5229,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
radv_pipeline_init_gs_ring_state(pipeline, &gs->info.gs_ring_info);
}
if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) {
radv_pipeline_init_tess_state(pipeline, &state);
}
if (!radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
radv_pipeline_init_vertex_input_state(pipeline, &state);

1
src/amd/vulkan/radv_private.h
View File

@@ -2021,7 +2021,6 @@ struct radv_graphics_pipeline {
uint8_t next_vertex_stage : 8;
uint32_t vb_desc_usage_mask;
uint32_t vb_desc_alloc_size;
uint32_t vgt_tf_param;
uint32_t pa_sc_mode_cntl_1;
uint32_t db_render_control;