radv: rework how the number of VGPRs is computed
Just a cleanup, it shouldn't change anything. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
@@ -2191,14 +2191,6 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
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buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
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buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
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LLVMConstInt(ctx->ac.i32, divisor, 0), "");
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LLVMConstInt(ctx->ac.i32, divisor, 0), "");
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}
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}
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if (ctx->options->key.vs.as_ls) {
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ctx->shader_info->vs.vgpr_comp_cnt =
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MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
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} else {
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ctx->shader_info->vs.vgpr_comp_cnt =
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MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
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}
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} else {
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} else {
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buffer_index = ctx->ac.i32_0;
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buffer_index = ctx->ac.i32_0;
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}
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}
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@@ -3047,8 +3039,6 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
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LLVMValueRef values[4];
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LLVMValueRef values[4];
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values[0] = ctx->vs_prim_id;
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values[0] = ctx->vs_prim_id;
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ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
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ctx->shader_info->vs.vgpr_comp_cnt);
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for (unsigned j = 1; j < 4; j++)
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for (unsigned j = 1; j < 4; j++)
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values[j] = ctx->ac.f32_0;
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values[j] = ctx->ac.f32_0;
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@@ -3756,15 +3746,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
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ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
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ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
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ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
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ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
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} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
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} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
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if (shader_info->info.vs.needs_instance_id) {
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if (ctx.options->key.vs.as_ls) {
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ctx.shader_info->vs.vgpr_comp_cnt =
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MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
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} else {
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ctx.shader_info->vs.vgpr_comp_cnt =
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MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
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}
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}
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ctx.abi.load_base_vertex = radv_load_base_vertex;
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ctx.abi.load_base_vertex = radv_load_base_vertex;
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} else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
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} else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
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shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
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shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
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@@ -3999,9 +3980,6 @@ ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_sha
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case MESA_SHADER_VERTEX:
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case MESA_SHADER_VERTEX:
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shader_info->vs.as_es = options->key.vs.as_es;
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shader_info->vs.as_es = options->key.vs.as_es;
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shader_info->vs.as_ls = options->key.vs.as_ls;
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shader_info->vs.as_ls = options->key.vs.as_ls;
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/* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
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if (options->key.vs.as_ls)
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shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
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break;
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break;
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default:
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default:
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break;
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break;
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@@ -507,13 +507,40 @@ radv_fill_shader_variant(struct radv_device *device,
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break;
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break;
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case MESA_SHADER_TESS_CTRL:
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case MESA_SHADER_TESS_CTRL:
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if (device->physical_device->rad_info.chip_class >= GFX9) {
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if (device->physical_device->rad_info.chip_class >= GFX9) {
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vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
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/* We need at least 2 components for LS.
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* VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
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* StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
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*/
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vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
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} else {
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} else {
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variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
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variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
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}
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}
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break;
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break;
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case MESA_SHADER_VERTEX:
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case MESA_SHADER_VERTEX:
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vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
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if (variant->info.vs.as_ls) {
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assert(device->physical_device->rad_info.chip_class <= GFX8);
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/* We need at least 2 components for LS.
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* VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
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* StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
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*/
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vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
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} else if (variant->info.vs.as_es) {
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assert(device->physical_device->rad_info.chip_class <= GFX8);
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/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
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vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
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} else {
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/* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
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* If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
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* StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
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*/
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if (options->key.vs.export_prim_id) {
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vgpr_comp_cnt = 2;
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} else if (info->vs.needs_instance_id) {
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vgpr_comp_cnt = 1;
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} else {
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vgpr_comp_cnt = 0;
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}
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}
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break;
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break;
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case MESA_SHADER_FRAGMENT:
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case MESA_SHADER_FRAGMENT:
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case MESA_SHADER_GEOMETRY:
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case MESA_SHADER_GEOMETRY:
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@@ -539,7 +566,8 @@ radv_fill_shader_variant(struct radv_device *device,
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unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
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unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
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if (es_type == MESA_SHADER_VERTEX) {
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if (es_type == MESA_SHADER_VERTEX) {
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es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
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/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
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es_vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
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} else if (es_type == MESA_SHADER_TESS_EVAL) {
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} else if (es_type == MESA_SHADER_TESS_EVAL) {
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es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
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es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
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} else {
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} else {
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@@ -266,7 +266,6 @@ struct radv_shader_variant_info {
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struct {
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struct {
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struct radv_vs_output_info outinfo;
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struct radv_vs_output_info outinfo;
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struct radv_es_output_info es_info;
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struct radv_es_output_info es_info;
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unsigned vgpr_comp_cnt;
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bool as_es;
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bool as_es;
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bool as_ls;
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bool as_ls;
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} vs;
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} vs;
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