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radv: set amdgpu-32bit-address-high-bits LLVM attribute

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2018-05-16 16:02:04 +02:00
parent fe2649d3ad
commit d8a61d3232
3 changed files with 8 additions and 0 deletions
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6
src/amd/vulkan/radv_nir_to_llvm.c
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@@ -511,6 +511,12 @@ create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
} }
} }
if (options->address32_hi) {
ac_llvm_add_target_dep_function_attr(main_function,
"amdgpu-32bit-address-high-bits",
options->address32_hi);
}
if (max_workgroup_size) { if (max_workgroup_size) {
ac_llvm_add_target_dep_function_attr(main_function, ac_llvm_add_target_dep_function_attr(main_function,
"amdgpu-max-work-group-size", "amdgpu-max-work-group-size",

1
src/amd/vulkan/radv_shader.c
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@@ -482,6 +482,7 @@ shader_variant_create(struct radv_device *device,
device->instance->debug_flags & RADV_DEBUG_PREOPTIR; device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
options->record_llvm_ir = device->keep_shader_info; options->record_llvm_ir = device->keep_shader_info;
options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size; options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
options->address32_hi = device->physical_device->rad_info.address32_hi;
if (options->supports_spill) if (options->supports_spill)
tm_options |= AC_TM_SUPPORTS_SPILL; tm_options |= AC_TM_SUPPORTS_SPILL;

1
src/amd/vulkan/radv_shader.h
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@@ -123,6 +123,7 @@ struct radv_nir_compiler_options {
enum radeon_family family; enum radeon_family family;
enum chip_class chip_class; enum chip_class chip_class;
uint32_t tess_offchip_block_dw_size; uint32_t tess_offchip_block_dw_size;
uint32_t address32_hi;
}; };
enum radv_ud_index { enum radv_ud_index {