From d88aba89463957d25ea26c4be8a13562a47f5a39 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 25 Aug 2022 08:50:37 +0200 Subject: [PATCH] radv: make sure to emit BREAK_BATCH when color write enable is dynamic Color write enable can change CB_TARGET_MASK and emitting a BREAK_BATCH seems needed for binning. Though, this was broken if this enable bit changed dynamically for the same pipeline. Split the function to not increase CPU overhead. Found by inspection. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 49 ++++++++++++++++---------------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 09b0699d509..cf1bd263e7d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1395,33 +1395,11 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control; } -static void -radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer) -{ - if (!cmd_buffer->device->pbb_allowed) - return; - - struct radv_binning_settings *settings = &cmd_buffer->device->physical_device->binning_settings; - bool break_for_new_ps = - (!cmd_buffer->state.emitted_graphics_pipeline || - cmd_buffer->state.emitted_graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT] != - cmd_buffer->state.graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT]) && - (settings->context_states_per_bin > 1 || settings->persistent_states_per_bin > 1); - bool break_for_new_cb_target_mask = - (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE) && - settings->context_states_per_bin > 1; - - if (!break_for_new_ps && !break_for_new_cb_target_mask) - return; - - radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); -} - static void radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) { struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; + const struct radv_device *device = cmd_buffer->device; if (cmd_buffer->state.emitted_graphics_pipeline == pipeline) return; @@ -1497,7 +1475,18 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->state.context_roll_without_scissor_emitted = true; } - radv_emit_batch_break_on_new_ps(cmd_buffer); + if (device->pbb_allowed) { + struct radv_binning_settings *settings = &device->physical_device->binning_settings; + + if ((!cmd_buffer->state.emitted_graphics_pipeline || + cmd_buffer->state.emitted_graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT] != + cmd_buffer->state.graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT]) && + (settings->context_states_per_bin > 1 || settings->persistent_states_per_bin > 1)) { + /* Break the batch on PS changes. */ + radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); + } + } radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->base.slab_bo); @@ -7448,6 +7437,7 @@ static void radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info, bool pipeline_is_dirty) { + const struct radv_device *device = cmd_buffer->device; bool late_scissor_emission; if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) || @@ -7500,6 +7490,17 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r } } + if (device->pbb_allowed) { + struct radv_binning_settings *settings = &device->physical_device->binning_settings; + + if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE) && + settings->context_states_per_bin > 1) { + /* Break the batch on CB_TARGET_MASK changes. */ + radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); + } + } + radv_cmd_buffer_flush_dynamic_state(cmd_buffer, pipeline_is_dirty); radv_emit_draw_registers(cmd_buffer, info);