freedreno/fdl: Add base_align
Tell users what the base address of the image needs to be aligned to. These values are based on experimentation via passing an offset to vkBindImageMemory with turnip and seeing if tests still pass. Note that r8g8 is also special in this regard, however it actually has an increased alignment (in bytes). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4357>
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@@ -36,26 +36,27 @@
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* missing 96/128 CPP for 8x MSAA with 32_32_32/32_32_32_32
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*/
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static const struct {
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unsigned basealign;
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unsigned pitchalign;
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unsigned heightalign;
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uint8_t ubwc_blockwidth;
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uint8_t ubwc_blockheight;
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} tile_alignment[] = {
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[1] = { 128, 32, 16, 4 },
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[2] = { 128, 16, 16, 4 },
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[3] = { 64, 32 },
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[4] = { 64, 16, 16, 4 },
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[6] = { 64, 16 },
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[8] = { 64, 16, 8, 4, },
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[12] = { 64, 16 },
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[16] = { 64, 16, 4, 4, },
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[24] = { 64, 16 },
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[32] = { 64, 16, 4, 2 },
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[48] = { 64, 16 },
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[64] = { 64, 16 },
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[1] = { 64, 128, 32, 16, 4 },
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[2] = { 128, 128, 16, 16, 4 },
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[3] = { 256, 64, 32 },
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[4] = { 256, 64, 16, 16, 4 },
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[6] = { 256, 64, 16 },
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[8] = { 256, 64, 16, 8, 4, },
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[12] = { 256, 64, 16 },
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[16] = { 256, 64, 16, 4, 4, },
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[24] = { 256, 64, 16 },
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[32] = { 256, 64, 16, 4, 2 },
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[48] = { 256, 64, 16 },
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[64] = { 256, 64, 16 },
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/* special cases for r8g8: */
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[0] = { 64, 32, 16, 4 },
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[0] = { 256, 64, 32, 16, 4 },
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};
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#define RGB_TILE_WIDTH_ALIGNMENT 64
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@@ -117,6 +118,12 @@ fdl6_layout(struct fdl_layout *layout,
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debug_assert(ta < ARRAY_SIZE(tile_alignment));
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debug_assert(tile_alignment[ta].pitchalign);
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if (layout->tile_mode) {
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layout->base_align = tile_alignment[ta].basealign;
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} else {
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layout->base_align = 64;
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}
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for (uint32_t level = 0; level < mip_levels; level++) {
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struct fdl_slice *slice = &layout->slices[level];
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struct fdl_slice *ubwc_slice = &layout->ubwc_slices[level];
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@@ -114,6 +114,7 @@ struct fdl_layout {
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enum pipe_format format;
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uint32_t size; /* Size of the whole image, in bytes. */
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uint32_t base_align; /* Alignment of the base address, in bytes. */
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};
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static inline uint32_t
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