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gallium/drivers: set force_indirect_unrolling_sampler for all required drivers

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This is set to true for all drivers that have a GLSL level
of support lower than 4.00. This matches the rule for setting the
GLSL IR option EmitNoIndirectSampler.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
This commit is contained in:
Timothy Arceri
2022-05-11 22:44:44 +10:00
committed by Marge Bot
parent ff8ddcb23e
commit d7a071a28f
14 changed files with 38 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/asahi/compiler/agx_compile.h
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@@ -224,6 +224,7 @@ static const nir_shader_compiler_options agx_nir_options = {
.has_fsub = true,
.has_isub = true,
.lower_uniforms_to_ubo = true,
.force_indirect_unrolling_sampler = true,
.force_indirect_unrolling = (nir_var_shader_in | nir_var_shader_out | nir_var_function_temp),
.lower_int64_options = (nir_lower_int64_options) ~(nir_lower_iadd64 | nir_lower_imul_2x32_64),
.lower_doubles_options = nir_lower_dmod,

2
src/freedreno/ir3/ir3_compiler.c
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@@ -115,6 +115,7 @@ static const nir_shader_compiler_options nir_options = {
.has_isub = true,
.lower_wpos_pntc = true,
.lower_cs_local_index_to_id = true,
.force_indirect_unrolling_sampler = true,
/* Only needed for the spirv_to_nir() pass done in ir3_cmdline.c
* but that should be harmless for GL since 64b is not
@@ -172,6 +173,7 @@ static const nir_shader_compiler_options nir_options_a6xx = {
.has_isub = true,
.max_unroll_iterations = 32,
.force_indirect_unrolling = nir_var_all,
.force_indirect_unrolling_sampler = true,
.lower_wpos_pntc = true,
.lower_cs_local_index_to_id = true,

7
src/gallium/auxiliary/nir/nir_to_tgsi.c
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@@ -3527,6 +3527,9 @@ ntt_fix_nir_options(struct pipe_screen *screen, struct nir_shader *s,
!screen->get_shader_param(screen, pipe_shader_type_from_mesa(s->info.stage),
PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
bool force_indirect_unrolling_sampler =
screen->get_param(screen, PIPE_CAP_GLSL_FEATURE_LEVEL) < 400;
nir_variable_mode no_indirects_mask = ntt_no_indirects_mask(s, screen);
if (!options->lower_extract_byte ||
@@ -3540,7 +3543,8 @@ ntt_fix_nir_options(struct pipe_screen *screen, struct nir_shader *s,
!options->lower_uniforms_to_ubo ||
!options->lower_vector_cmp ||
options->lower_fsqrt != lower_fsqrt ||
options->force_indirect_unrolling != no_indirects_mask) {
options->force_indirect_unrolling != no_indirects_mask ||
force_indirect_unrolling_sampler) {
nir_shader_compiler_options *new_options = ralloc(s, nir_shader_compiler_options);
*new_options = *s->options;
@@ -3556,6 +3560,7 @@ ntt_fix_nir_options(struct pipe_screen *screen, struct nir_shader *s,
new_options->lower_vector_cmp = true;
new_options->lower_fsqrt = lower_fsqrt;
new_options->force_indirect_unrolling = no_indirects_mask;
new_options->force_indirect_unrolling_sampler = force_indirect_unrolling_sampler;
s->options = new_options;
}

1
src/gallium/drivers/freedreno/a2xx/ir2_nir.c
View File

@@ -50,6 +50,7 @@ static const nir_shader_compiler_options options = {
.lower_insert_byte = true,
.lower_insert_word = true,
.force_indirect_unrolling = nir_var_all,
.force_indirect_unrolling_sampler = true,
};
const nir_shader_compiler_options *

1
src/gallium/drivers/i915/i915_screen.c
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@@ -121,6 +121,7 @@ static const nir_shader_compiler_options i915_compiler_options = {
.lower_vector_cmp = true,
.use_interpolated_input_intrinsics = true,
.force_indirect_unrolling = ~0,
.force_indirect_unrolling_sampler = true,
};
static const struct nir_shader_compiler_options gallivm_nir_options = {

2
src/gallium/drivers/lima/lima_program.c
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@@ -62,6 +62,7 @@ static const nir_shader_compiler_options vs_nir_options = {
.lower_insert_byte = true,
.lower_insert_word = true,
.force_indirect_unrolling = (nir_var_shader_in | nir_var_shader_out | nir_var_function_temp),
.force_indirect_unrolling_sampler = true,
.lower_varying_from_uniform = true,
};
@@ -83,6 +84,7 @@ static const nir_shader_compiler_options fs_nir_options = {
.lower_bitops = true,
.lower_vector_cmp = true,
.force_indirect_unrolling = (nir_var_shader_in | nir_var_shader_out | nir_var_function_temp),
.force_indirect_unrolling_sampler = true,
.lower_varying_from_uniform = true,
};

1
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
View File

@@ -3379,6 +3379,7 @@ nvir_nir_shader_compiler_options(int chipset)
op.lower_rotate = (chipset < NVISA_GV100_CHIPSET);
op.has_imul24 = false;
op.intel_vec4 = false;
op.force_indirect_unrolling_sampler = (chipset < NVISA_GF100_CHIPSET),
op.max_unroll_iterations = 32;
op.lower_int64_options = (nir_lower_int64_options) (
((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul64 : 0) |

1
src/gallium/drivers/nouveau/nv30/nv30_screen.c
View File

@@ -496,6 +496,7 @@ static const nir_shader_compiler_options nv30_base_compiler_options = {
.lower_rotate = true,
.lower_uniforms_to_ubo = true,
.lower_vector_cmp = true,
.force_indirect_unrolling_sampler = true,
.max_unroll_iterations = 32,
.use_interpolated_input_intrinsics = true,

3
src/gallium/drivers/r600/r600_pipe_common.c
View File

@@ -1364,6 +1364,9 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
* lowered code */
rscreen->nir_options.lower_fpow = rscreen->debug_flags & DBG_NIR_PREFERRED;
if (rscreen->info.family < CHIP_CEDAR)
rscreen->nir_options.force_indirect_unrolling_sampler = true;
if (rscreen->info.gfx_level < EVERGREEN) {
/* Pre-EG doesn't have these ALU ops */
rscreen->nir_options.lower_bit_count = true;

20
src/gallium/drivers/svga/svga_screen.c
View File

@@ -770,16 +770,26 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
.max_unroll_iterations = 32, \
.use_interpolated_input_intrinsics = true
#define VGPU10_OPTIONS \
.lower_doubles_options = nir_lower_dfloor, \
.lower_fmod = true, \
.lower_fpow = true
static const nir_shader_compiler_options svga_vgpu9_compiler_options = {
COMMON_OPTIONS,
.lower_bitops = true,
.force_indirect_unrolling_sampler = true,
};
static const nir_shader_compiler_options svga_vgpu10_compiler_options = {
COMMON_OPTIONS,
.lower_doubles_options = nir_lower_dfloor,
.lower_fmod = true,
.lower_fpow = true,
VGPU10_OPTIONS,
.force_indirect_unrolling_sampler = true,
};
static const nir_shader_compiler_options svga_gl4_compiler_options = {
COMMON_OPTIONS,
VGPU10_OPTIONS,
};
static const void *
@@ -792,7 +802,9 @@ svga_get_compiler_options(struct pipe_screen *pscreen,
assert(ir == PIPE_SHADER_IR_NIR);
if (sws->have_vgpu10)
if (sws->have_gl43 || sws->have_sm5)
return &svga_gl4_compiler_options;
else if (sws->have_vgpu10)
return &svga_vgpu10_compiler_options;
else
return &svga_vgpu9_compiler_options;

1
src/gallium/drivers/v3d/v3d_screen.c
View File

@@ -738,6 +738,7 @@ static const nir_shader_compiler_options v3d_nir_options = {
* limit register pressure impact.
*/
.max_unroll_iterations = 16,
.force_indirect_unrolling_sampler = true,
};
static const void *

1
src/intel/compiler/brw_compiler.c
View File

@@ -194,6 +194,7 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
nir_options->force_indirect_unrolling |=
brw_nir_no_indirect_mask(compiler, i);
nir_options->force_indirect_unrolling_sampler = devinfo->ver < 7;
if (compiler->use_tcs_8_patch) {
/* TCS 8_PATCH mode has multiple patches per subgroup */

1
src/panfrost/bifrost/bifrost_compile.h
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@@ -93,6 +93,7 @@ static const nir_shader_compiler_options bifrost_nir_options = {
.lower_cs_local_index_to_id = true,
.max_unroll_iterations = 32,
.force_indirect_unrolling = (nir_var_shader_in | nir_var_shader_out | nir_var_function_temp),
.force_indirect_unrolling_sampler = true,
};
#endif

1
src/panfrost/midgard/midgard_compile.h
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@@ -97,6 +97,7 @@ static const nir_shader_compiler_options midgard_nir_options = {
.lower_cs_local_index_to_id = true,
.max_unroll_iterations = 32,
.force_indirect_unrolling = (nir_var_shader_in | nir_var_shader_out | nir_var_function_temp),
.force_indirect_unrolling_sampler = true,
};
#endif