From d777cbf66c1320e03dcc2e579909f1f3be3d15fe Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 30 Jan 2024 11:08:41 +0100 Subject: [PATCH] radv: add a new user SGPR for the ESGS ring item size With shader object, when VS+GS or TES+GS are compiled separately and the VS has written (but unused) outputs, the ESGS vertex stride must be passed through an user SGPR. This is because when the GS is compiled we can't know the number of ES outputs. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_shader.h | 11 ++++++----- src/amd/vulkan/radv_shader_args.c | 5 ++++- src/amd/vulkan/radv_shader_args.h | 3 +++ 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 8c307078c33..abb0f189b45 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -211,11 +211,12 @@ enum radv_ud_index { AC_UD_NGG_PROVOKING_VTX = 7, AC_UD_NGG_CULLING_SETTINGS = 8, AC_UD_NGG_VIEWPORT = 9, - AC_UD_FORCE_VRS_RATES = 10, - AC_UD_TASK_RING_ENTRY = 11, - AC_UD_NUM_VERTS_PER_PRIM = 12, - AC_UD_NEXT_STAGE_PC = 13, - AC_UD_SHADER_START = 14, + AC_UD_VGT_ESGS_RING_ITEMSIZE = 10, + AC_UD_FORCE_VRS_RATES = 11, + AC_UD_TASK_RING_ENTRY = 12, + AC_UD_NUM_VERTS_PER_PRIM = 13, + AC_UD_NEXT_STAGE_PC = 14, + AC_UD_SHADER_START = 15, AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START, AC_UD_VS_BASE_VERTEX_START_INSTANCE, AC_UD_VS_PROLOG_INPUTS, diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c index 513aa5e97d6..3e0ec58ce8a 100644 --- a/src/amd/vulkan/radv_shader_args.c +++ b/src/amd/vulkan/radv_shader_args.c @@ -707,8 +707,10 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics declare_ngg_sgprs(info, args, has_ngg_provoking_vtx); } - if (info->merged_shader_compiled_separately) + if (info->merged_shader_compiled_separately) { + add_ud_arg(args, 1, AC_ARG_INT, &args->vgt_esgs_ring_itemsize, AC_UD_VGT_ESGS_RING_ITEMSIZE); add_ud_arg(args, 1, AC_ARG_INT, &args->next_stage_pc, AC_UD_NEXT_STAGE_PC); + } if (previous_stage != MESA_SHADER_MESH || !device->mesh_fast_launch_2) { ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[0]); @@ -749,6 +751,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics ac_add_preserved(&args->ac, &args->shader_query_state); if (info->is_ngg) ac_add_preserved(&args->ac, &args->ngg_provoking_vtx); + ac_add_preserved(&args->ac, &args->vgt_esgs_ring_itemsize); /* VGPRs */ ac_add_preserved(&args->ac, &args->ac.gs_vtx_offset[0]); diff --git a/src/amd/vulkan/radv_shader_args.h b/src/amd/vulkan/radv_shader_args.h index 5327affbc3a..59a7c844cd3 100644 --- a/src/amd/vulkan/radv_shader_args.h +++ b/src/amd/vulkan/radv_shader_args.h @@ -86,6 +86,9 @@ struct radv_shader_args { */ struct ac_arg tes_state; + /* GS */ + struct ac_arg vgt_esgs_ring_itemsize; + /* NGG VS streamout */ struct ac_arg num_verts_per_prim;