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radv: add radv_meta_init_shader

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14087>
This commit is contained in:
Rhys Perry
2021-12-06 18:21:11 +00:00
committed by Marge Bot
parent c2550d1b7c
commit d74498e617
20 changed files with 76 additions and 78 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/amd/vulkan/radv_acceleration_structure.c
View File

@@ -916,8 +916,7 @@ static nir_shader *
build_leaf_shader(struct radv_device *dev)
{
const struct glsl_type *vec3_type = glsl_vector_type(GLSL_TYPE_FLOAT, 3);
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "accel_build_leaf_shader");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_build_leaf_shader");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
@@ -1262,8 +1261,7 @@ static nir_shader *
build_internal_shader(struct radv_device *dev)
{
const struct glsl_type *vec3_type = glsl_vector_type(GLSL_TYPE_FLOAT, 3);
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "accel_build_internal_shader");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_build_internal_shader");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
@@ -1375,7 +1373,7 @@ struct copy_constants {
static nir_shader *
build_copy_shader(struct radv_device *dev)
{
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "accel_copy");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_copy");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;

19
src/amd/vulkan/radv_meta.c
View File

@@ -554,6 +554,19 @@ radv_device_finish_meta(struct radv_device *device)
mtx_destroy(&device->meta_state.mtx);
}
nir_builder PRINTFLIKE(2, 3) radv_meta_init_shader(gl_shader_stage stage, const char *name, ...)
{
nir_builder b = nir_builder_init_simple_shader(stage, NULL, NULL);
if (name) {
va_list args;
va_start(args, name);
b.shader->info.name = ralloc_vasprintf(b.shader, name, args);
va_end(args);
}
return b;
}
nir_ssa_def *
radv_meta_gen_rect_vertices_comp2(nir_builder *vs_b, nir_ssa_def *comp2)
{
@@ -594,7 +607,7 @@ radv_meta_build_nir_vs_generate_vertices(void)
nir_variable *v_position;
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_VERTEX, NULL, "meta_vs_gen_verts");
nir_builder b = radv_meta_init_shader(MESA_SHADER_VERTEX, "meta_vs_gen_verts");
nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
@@ -609,9 +622,7 @@ radv_meta_build_nir_vs_generate_vertices(void)
nir_shader *
radv_meta_build_nir_fs_noop(void)
{
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL, "meta_noop_fs");
return b.shader;
return radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_noop_fs").shader;
}
void

1
src/amd/vulkan/radv_meta.h
View File

@@ -289,6 +289,7 @@ radv_is_dcc_decompress_pipeline(struct radv_cmd_buffer *cmd_buffer)
/* common nir builder helpers */
#include "nir/nir_builder.h"
nir_builder PRINTFLIKE(2, 3) radv_meta_init_shader(gl_shader_stage stage, const char *name, ...);
nir_ssa_def *radv_meta_gen_rect_vertices(nir_builder *vs_b);
nir_ssa_def *radv_meta_gen_rect_vertices_comp2(nir_builder *vs_b, nir_ssa_def *comp2);
nir_shader *radv_meta_build_nir_vs_generate_vertices(void);

11
src/amd/vulkan/radv_meta_blit.c
View File

@@ -39,7 +39,7 @@ static nir_shader *
build_nir_vertex_shader(void)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_VERTEX, NULL, "meta_blit_vs");
nir_builder b = radv_meta_init_shader(MESA_SHADER_VERTEX, "meta_blit_vs");
nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
pos_out->data.location = VARYING_SLOT_POS;
@@ -82,8 +82,7 @@ static nir_shader *
build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL, "meta_blit_fs.%d", tex_dim);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_blit_fs.%d", tex_dim);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -130,8 +129,7 @@ static nir_shader *
build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL, "meta_blit_depth_fs.%d", tex_dim);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_blit_depth_fs.%d", tex_dim);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -178,8 +176,7 @@ static nir_shader *
build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL,
"meta_blit_stencil_fs.%d", tex_dim);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_blit_stencil_fs.%d", tex_dim);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;

8
src/amd/vulkan/radv_meta_blit2d.c
View File

@@ -425,7 +425,7 @@ build_nir_vertex_shader(void)
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_VERTEX, NULL, "meta_blit2d_vs");
nir_builder b = radv_meta_init_shader(MESA_SHADER_VERTEX, "meta_blit2d_vs");
nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
pos_out->data.location = VARYING_SLOT_POS;
@@ -562,7 +562,7 @@ build_nir_copy_fragment_shader(struct radv_device *device, texel_fetch_build_fun
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL, "%s", name);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "%s", name);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -585,7 +585,7 @@ build_nir_copy_fragment_shader_depth(struct radv_device *device, texel_fetch_bui
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL, "%s", name);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "%s", name);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -608,7 +608,7 @@ build_nir_copy_fragment_shader_stencil(struct radv_device *device, texel_fetch_b
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL, "%s", name);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "%s", name);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;

4
src/amd/vulkan/radv_meta_buffer.c
View File

@@ -7,7 +7,7 @@
static nir_shader *
build_buffer_fill_shader(struct radv_device *dev)
{
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_buffer_fill");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_buffer_fill");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
@@ -31,7 +31,7 @@ build_buffer_fill_shader(struct radv_device *dev)
static nir_shader *
build_buffer_copy_shader(struct radv_device *dev)
{
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_buffer_copy");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_buffer_copy");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;

25
src/amd/vulkan/radv_meta_bufimage.c
View File

@@ -38,8 +38,8 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
const struct glsl_type *sampler_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL,
is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
nir_builder b =
radv_meta_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
@@ -220,8 +220,8 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
const struct glsl_type *buf_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL,
is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
nir_builder b =
radv_meta_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
@@ -400,8 +400,7 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev)
const struct glsl_type *buf_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_btoi_r32g32b32_cs");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_btoi_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
@@ -554,8 +553,8 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d, int samples)
: GLSL_SAMPLER_DIM_2D;
const struct glsl_type *buf_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
nir_builder b = nir_builder_init_simple_shader(
MESA_SHADER_COMPUTE, NULL, is_3d ? "meta_itoi_cs_3d-%d" : "meta_itoi_cs-%d", samples);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE,
is_3d ? "meta_itoi_cs_3d-%d" : "meta_itoi_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
@@ -754,8 +753,7 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev)
const struct glsl_type *type =
glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_itoi_r32g32b32_cs");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_itoi_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
@@ -914,8 +912,8 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples
: is_multisampled ? GLSL_SAMPLER_DIM_MS
: GLSL_SAMPLER_DIM_2D;
const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
nir_builder b = nir_builder_init_simple_shader(
MESA_SHADER_COMPUTE, NULL, is_3d ? "meta_cleari_cs_3d-%d" : "meta_cleari_cs-%d", samples);
nir_builder b = radv_meta_init_shader(
MESA_SHADER_COMPUTE, is_3d ? "meta_cleari_cs_3d-%d" : "meta_cleari_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
@@ -1072,8 +1070,7 @@ static nir_shader *
build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev)
{
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_cleari_r32g32b32_cs");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_cleari_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;

23
src/amd/vulkan/radv_meta_clear.c
View File

@@ -34,10 +34,9 @@ enum { DEPTH_CLEAR_SLOW, DEPTH_CLEAR_FAST };
static void
build_color_shaders(struct nir_shader **out_vs, struct nir_shader **out_fs, uint32_t frag_output)
{
nir_builder vs_b =
nir_builder_init_simple_shader(MESA_SHADER_VERTEX, NULL, "meta_clear_color_vs");
nir_builder fs_b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL,
"meta_clear_color_fs-%d", frag_output);
nir_builder vs_b = radv_meta_init_shader(MESA_SHADER_VERTEX, "meta_clear_color_vs");
nir_builder fs_b =
radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_clear_color_fs-%d", frag_output);
const struct glsl_type *position_type = glsl_vec4_type();
const struct glsl_type *color_type = glsl_vec4_type();
@@ -473,11 +472,11 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachment *cl
static void
build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs, bool unrestricted)
{
nir_builder vs_b = nir_builder_init_simple_shader(
MESA_SHADER_VERTEX, NULL,
nir_builder vs_b = radv_meta_init_shader(
MESA_SHADER_VERTEX,
unrestricted ? "meta_clear_depthstencil_unrestricted_vs" : "meta_clear_depthstencil_vs");
nir_builder fs_b = nir_builder_init_simple_shader(
MESA_SHADER_FRAGMENT, NULL,
nir_builder fs_b = radv_meta_init_shader(
MESA_SHADER_FRAGMENT,
unrestricted ? "meta_clear_depthstencil_unrestricted_fs" : "meta_clear_depthstencil_fs");
const struct glsl_type *position_out_type = glsl_vec4_type();
@@ -1059,8 +1058,7 @@ radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_imag
static nir_shader *
build_clear_htile_mask_shader()
{
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_clear_htile_mask");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_clear_htile_mask");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
@@ -1163,9 +1161,8 @@ build_clear_dcc_comp_to_single_shader(bool is_msaa)
enum glsl_sampler_dim dim = is_msaa ? GLSL_SAMPLER_DIM_MS : GLSL_SAMPLER_DIM_2D;
const struct glsl_type *img_type = glsl_image_type(dim, true, GLSL_TYPE_FLOAT);
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_clear_dcc_comp_to_single-%s",
is_msaa ? "multisampled" : "singlesampled");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_clear_dcc_comp_to_single-%s",
is_msaa ? "multisampled" : "singlesampled");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;

2
src/amd/vulkan/radv_meta_copy_vrs_htile.c
View File

@@ -44,7 +44,7 @@ radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device)
static nir_shader *
build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf)
{
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_copy_vrs_htile");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;

2
src/amd/vulkan/radv_meta_dcc_retile.c
View File

@@ -32,7 +32,7 @@ build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *sur
{
enum glsl_sampler_dim dim = GLSL_SAMPLER_DIM_BUF;
const struct glsl_type *buf_type = glsl_image_type(dim, false, GLSL_TYPE_UINT);
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "dcc_retile_compute");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "dcc_retile_compute");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;

3
src/amd/vulkan/radv_meta_decompress.c
View File

@@ -38,8 +38,7 @@ build_expand_depth_stencil_compute_shader(struct radv_device *dev)
{
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "expand_depth_stencil_compute");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "expand_depth_stencil_compute");
/* We need at least 8/8/1 to cover an entire HTILE block in a single workgroup. */
b.shader->info.workgroup_size[0] = 8;

3
src/amd/vulkan/radv_meta_fast_clear.c
View File

@@ -39,8 +39,7 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
{
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "dcc_decompress_compute");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "dcc_decompress_compute");
/* We need at least 16/16/1 to cover an entire DCC block in a single workgroup. */
b.shader->info.workgroup_size[0] = 16;

2
src/amd/vulkan/radv_meta_fmask_copy.c
View File

@@ -29,7 +29,7 @@ build_fmask_copy_compute_shader(struct radv_device *dev, int samples)
const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, false, GLSL_TYPE_FLOAT);
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_fmask_copy_cs_-%d", samples);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_fmask_copy_cs_-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;

3
src/amd/vulkan/radv_meta_fmask_expand.c
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@@ -33,8 +33,7 @@ build_fmask_expand_compute_shader(struct radv_device *device, int samples)
glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, true, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, true, GLSL_TYPE_FLOAT);
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_fmask_expand_cs-%d", samples);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_fmask_expand_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;

2
src/amd/vulkan/radv_meta_resolve.c
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@@ -37,7 +37,7 @@ build_nir_fs(void)
const struct glsl_type *vec4 = glsl_vec4_type();
nir_variable *f_color; /* vec4, fragment output color */
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL, "meta_resolve_fs");
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_resolve_fs");
f_color = nir_variable_create(b.shader, nir_var_shader_out, vec4, "f_color");
f_color->data.location = FRAG_RESULT_DATA0;

11
src/amd/vulkan/radv_meta_resolve_cs.c
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@@ -64,9 +64,8 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
const struct glsl_type *sampler_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_resolve_cs-%d-%s", samples,
is_integer ? "int" : (is_srgb ? "srgb" : "float"));
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_resolve_cs-%d-%s", samples,
is_integer ? "int" : (is_srgb ? "srgb" : "float"));
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
@@ -136,9 +135,9 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, true, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, true, GLSL_TYPE_FLOAT);
nir_builder b = nir_builder_init_simple_shader(
MESA_SHADER_COMPUTE, NULL, "meta_resolve_cs_%s-%s-%d",
index == DEPTH_RESOLVE ? "depth" : "stencil", get_resolve_mode_str(resolve_mode), samples);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_resolve_cs_%s-%s-%d",
index == DEPTH_RESOLVE ? "depth" : "stencil",
get_resolve_mode_str(resolve_mode), samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;

12
src/amd/vulkan/radv_meta_resolve_fs.c
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@@ -34,7 +34,7 @@ static nir_shader *
build_nir_vertex_shader(void)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_VERTEX, NULL, "meta_resolve_vs");
nir_builder b = radv_meta_init_shader(MESA_SHADER_VERTEX, "meta_resolve_vs");
nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
pos_out->data.location = VARYING_SLOT_POS;
@@ -52,8 +52,8 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samp
const struct glsl_type *sampler_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
nir_builder b = nir_builder_init_simple_shader(
MESA_SHADER_FRAGMENT, NULL, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : "float");
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_resolve_fs-%d-%s", samples,
is_integer ? "int" : "float");
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
input_img->data.descriptor_set = 0;
@@ -329,9 +329,9 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
const struct glsl_type *sampler_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_FLOAT);
nir_builder b = nir_builder_init_simple_shader(
MESA_SHADER_FRAGMENT, NULL, "meta_resolve_fs_%s-%s-%d",
index == DEPTH_RESOLVE ? "depth" : "stencil", get_resolve_mode_str(resolve_mode), samples);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_resolve_fs_%s-%s-%d",
index == DEPTH_RESOLVE ? "depth" : "stencil",
get_resolve_mode_str(resolve_mode), samples);
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
input_img->data.descriptor_set = 0;

3
src/amd/vulkan/radv_pipeline.c
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@@ -34,6 +34,7 @@
#include "util/u_atomic.h"
#include "radv_cs.h"
#include "radv_debug.h"
#include "radv_meta.h"
#include "radv_private.h"
#include "radv_shader.h"
#include "vk_util.h"
@@ -3545,7 +3546,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
}
if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
nir_builder fs_b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, NULL, "noop_fs");
nir_builder fs_b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "noop_fs");
fs_m = vk_shader_module_from_nir(fs_b.shader);
modules[MESA_SHADER_FRAGMENT] = &fs_m;
}

9
src/amd/vulkan/radv_query.c
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@@ -117,7 +117,7 @@ build_occlusion_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "occlusion_query");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "occlusion_query");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
@@ -255,8 +255,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "pipeline_statistics_query");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "pipeline_statistics_query");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
@@ -396,7 +395,7 @@ build_tfb_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "tfb_query");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "tfb_query");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
@@ -521,7 +520,7 @@ build_timestamp_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "timestamp_query");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "timestamp_query");
b.shader->info.workgroup_size[0] = 64;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;

3
src/amd/vulkan/radv_shader.c
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@@ -33,6 +33,7 @@
#include "util/mesa-sha1.h"
#include "util/u_atomic.h"
#include "radv_debug.h"
#include "radv_meta.h"
#include "radv_private.h"
#include "radv_shader_args.h"
@@ -1919,7 +1920,7 @@ radv_create_trap_handler_shader(struct radv_device *device)
struct radv_shader_binary *binary = NULL;
struct radv_shader_info info = {0};
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_trap_handler");
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_trap_handler");
options.explicit_scratch_args = true;
options.wgp_mode = radv_should_use_wgp_mode(device, MESA_SHADER_COMPUTE, &info);