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radeonsi/nir: Fix type in bindless address computation

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Bindless handles in GL are 64-bit. This fixes an assert failure in LLVM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Connor Abbott
2019-05-24 15:08:06 +02:00
parent a6e879984c
commit d68218dbca
1 changed files with 2 additions and 2 deletions
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4
src/gallium/drivers/radeonsi/si_shader_nir.c
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@@ -1020,7 +1020,7 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
* 16-dword slots for now.
*/
dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
LLVMConstInt(ctx->i32, 2, 0), "");
LLVMConstInt(ctx->i64, 2, 0), "");
return si_load_image_desc(ctx, list, dynamic_index, desc_type,
dcc_off, true);
@@ -1032,7 +1032,7 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
* to prevent incorrect code generation and hangs.
*/
dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
LLVMConstInt(ctx->i32, 2, 0), "");
LLVMConstInt(ctx->i64, 2, 0), "");
list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
}