ir3/isa: fix cat3-alt immed src

The override used for the immed encoding in #cat3-src-const-or-immed
used a pattern which isn't supported in overrides by isaspec. The
pattern in the base bitset (10) was too strict for immediates since it
didn't allow the most significant bit to be 1.

Fix this by making the base pattern 1 and adding an assert for the next
bit to be 0 in the non-immed case.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 1c6c200c0d ("ir3: add newly found shlg.b16 instruction")
(cherry picked from commit 943f666b69)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>

.pick_status.json

@@ -454,7 +454,7 @@
         "description": "ir3/isa: fix cat3-alt immed src",
         "nominated": true,
         "nomination_type": 2,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "1c6c200c0d79329174d19ae694d11f762819eeba",
         "notes": null

src/freedreno/ir3/tests/disasm.c

@@ -125,6 +125,7 @@ static const struct test {
    INSTR_6XX(65900820_0c0aac05, "(nop3) shlg hr8.x, hc<a0.x + 5>, hr8.x, hc<a0.x + 10>"), /* not seen in blob */
    INSTR_6XX(65ae0c5c_0002a001, "(nop3) shlg r23.x, r0.y, r23.x, r0.z"), /* (nop3) shlg.b32 r23.x, (r)r0.y, (r)r23.x, r0.z */
    INSTR_6XX(64018802_0002e003, "(nop3) shrm hr0.z, (neg)hr0.w, hr0.w, hr0.z"),
+   INSTR_6XX(646084c3_1fff300a, "shrm r48.w, 10, r48.y, 4095"),
    INSTR_6XX(64818802_0002e003, "(nop3) shlm hr0.z, (neg)hr0.w, hr0.w, hr0.z"),
    INSTR_6XX(65018802_0002e003, "(nop3) shrg hr0.z, (neg)hr0.w, hr0.w, hr0.z"),
    INSTR_6XX(66018802_0002e003, "(nop3) andg hr0.z, (neg)hr0.w, hr0.w, hr0.z"),

src/freedreno/isa/ir3-cat3.xml

@@ -60,7 +60,6 @@ SOFTWARE.
 			{IMMED}
 		</display>
 		<field name="IMMED" low="0" high="11" type="uint"/>
-		<pattern pos="12">1</pattern>
 	</override>
 
 	<display>
@@ -68,7 +67,8 @@ SOFTWARE.
 	</display>
 	<field name="SWIZ" low="0" high="1" type="#swiz"/>
 	<field name="CONST" low="2" high="10" type="uint"/>
-	<pattern low="11" high="12">10</pattern>
+	<pattern pos="12">1</pattern>
+	<assert pos="11">0</assert>
 	<encode>
 		<map name="CONST">src->num >> 2</map>
 		<map name="SWIZ">src->num &amp; 0x3</map>