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gallium/radeon: allow the winsys to choose the IB size

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Picked from the amdgpu branch.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák
2015-06-27 14:19:41 +02:00
parent 57245cce52
commit d587742650
11 changed files with 18 additions and 18 deletions
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2
src/gallium/drivers/r300/r300_blit.c
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@@ -382,7 +382,7 @@ static void r300_clear(struct pipe_context* pipe,
r300_get_num_cs_end_dwords(r300); r300_get_num_cs_end_dwords(r300);
/* Reserve CS space. */ /* Reserve CS space. */
if (dwords > (RADEON_MAX_CMDBUF_DWORDS - r300->cs->cdw)) { if (dwords > (r300->cs->max_dw - r300->cs->cdw)) {
r300_flush(&r300->context, RADEON_FLUSH_ASYNC, NULL); r300_flush(&r300->context, RADEON_FLUSH_ASYNC, NULL);
} }

2
src/gallium/drivers/r300/r300_cs.h
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@@ -46,7 +46,7 @@
#ifdef DEBUG #ifdef DEBUG
#define BEGIN_CS(size) do { \ #define BEGIN_CS(size) do { \
assert(size <= (RADEON_MAX_CMDBUF_DWORDS - cs_copy->cdw)); \ assert(size <= (cs_copy->max_dw - cs_copy->cdw)); \
cs_count = size; \ cs_count = size; \
} while (0) } while (0)

2
src/gallium/drivers/r300/r300_render.c
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@@ -215,7 +215,7 @@ static boolean r300_reserve_cs_dwords(struct r300_context *r300,
cs_dwords += r300_get_num_cs_end_dwords(r300); cs_dwords += r300_get_num_cs_end_dwords(r300);
/* Reserve requested CS space. */ /* Reserve requested CS space. */
if (cs_dwords > (RADEON_MAX_CMDBUF_DWORDS - r300->cs->cdw)) { if (cs_dwords > (r300->cs->max_dw - r300->cs->cdw)) {
r300_flush(&r300->context, RADEON_FLUSH_ASYNC, NULL); r300_flush(&r300->context, RADEON_FLUSH_ASYNC, NULL);
flushed = TRUE; flushed = TRUE;
} }

2
src/gallium/drivers/r600/r600_hw_context.c
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@@ -93,7 +93,7 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
num_dw += 10; num_dw += 10;
/* Flush if there's not enough space. */ /* Flush if there's not enough space. */
if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { if (num_dw > ctx->b.rings.gfx.cs->max_dw) {
ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL); ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
} }
} }

4
src/gallium/drivers/r600/r600_pipe.h
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@@ -493,7 +493,7 @@ struct r600_context {
static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs, static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
struct r600_command_buffer *cb) struct r600_command_buffer *cb)
{ {
assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS); assert(cs->cdw + cb->num_dw <= cs->max_dw);
memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw); memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
cs->cdw += cb->num_dw; cs->cdw += cb->num_dw;
} }
@@ -826,7 +826,7 @@ static inline void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *c
static inline void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) static inline void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{ {
assert(reg >= R600_CTL_CONST_OFFSET); assert(reg >= R600_CTL_CONST_OFFSET);
assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); assert(cs->cdw+2+num <= cs->max_dw);
cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
} }

8
src/gallium/drivers/radeon/r600_cs.h
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@@ -77,7 +77,7 @@ static inline void r600_emit_reloc(struct r600_common_context *rctx,
static inline void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) static inline void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{ {
assert(reg < R600_CONTEXT_REG_OFFSET); assert(reg < R600_CONTEXT_REG_OFFSET);
assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); assert(cs->cdw+2+num <= cs->max_dw);
radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2); radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
} }
@@ -91,7 +91,7 @@ static inline void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned r
static inline void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) static inline void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{ {
assert(reg >= R600_CONTEXT_REG_OFFSET); assert(reg >= R600_CONTEXT_REG_OFFSET);
assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); assert(cs->cdw+2+num <= cs->max_dw);
radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2); radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
} }
@@ -105,7 +105,7 @@ static inline void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned
static inline void si_write_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) static inline void si_write_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{ {
assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); assert(cs->cdw+2+num <= cs->max_dw);
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
} }
@@ -119,7 +119,7 @@ static inline void si_write_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, un
static inline void cik_write_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) static inline void cik_write_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{ {
assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); assert(cs->cdw+2+num <= cs->max_dw);
radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
} }

4
src/gallium/drivers/radeon/r600_pipe_common.c
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@@ -108,9 +108,9 @@ void r600_draw_rectangle(struct blitter_context *blitter,
void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw) void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
{ {
/* Flush if there's not enough space. */ /* Flush if there's not enough space. */
if ((num_dw + ctx->rings.dma.cs->cdw) > RADEON_MAX_CMDBUF_DWORDS) { if ((num_dw + ctx->rings.dma.cs->cdw) > ctx->rings.dma.cs->max_dw) {
ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL); ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
assert((num_dw + ctx->rings.dma.cs->cdw) <= RADEON_MAX_CMDBUF_DWORDS); assert((num_dw + ctx->rings.dma.cs->cdw) <= ctx->rings.dma.cs->max_dw);
} }
} }

3
src/gallium/drivers/radeon/radeon_winsys.h
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@@ -42,8 +42,6 @@
#include "pipebuffer/pb_buffer.h" #include "pipebuffer/pb_buffer.h"
#define RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
#define RADEON_FLUSH_ASYNC (1 << 0) #define RADEON_FLUSH_ASYNC (1 << 0)
#define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */ #define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */
#define RADEON_FLUSH_COMPUTE (1 << 2) #define RADEON_FLUSH_COMPUTE (1 << 2)
@@ -196,6 +194,7 @@ struct radeon_winsys_cs_handle;
struct radeon_winsys_cs { struct radeon_winsys_cs {
unsigned cdw; /* Number of used dwords. */ unsigned cdw; /* Number of used dwords. */
unsigned max_dw; /* Maximum number of dwords. */
uint32_t *buf; /* The command buffer. */ uint32_t *buf; /* The command buffer. */
enum ring_type ring_type; enum ring_type ring_type;
}; };

2
src/gallium/drivers/radeonsi/si_hw_context.c
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@@ -86,7 +86,7 @@ void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
#endif #endif
/* Flush if there's not enough space. */ /* Flush if there's not enough space. */
if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { if (num_dw > ctx->b.rings.gfx.cs->max_dw) {
ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL); ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
} }
} }

5
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
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@@ -188,6 +188,7 @@ radeon_drm_cs_create(struct radeon_winsys *rws,
cs->cst = &cs->csc2; cs->cst = &cs->csc2;
cs->base.buf = cs->csc->buf; cs->base.buf = cs->csc->buf;
cs->base.ring_type = ring_type; cs->base.ring_type = ring_type;
cs->base.max_dw = ARRAY_SIZE(cs->csc->buf);
p_atomic_inc(&ws->num_cs); p_atomic_inc(&ws->num_cs);
return &cs->base; return &cs->base;
@@ -467,7 +468,7 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
break; break;
} }
if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) { if (rcs->cdw > rcs->max_dw) {
fprintf(stderr, "radeon: command stream overflowed\n"); fprintf(stderr, "radeon: command stream overflowed\n");
} }
@@ -486,7 +487,7 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
cs->cst->cs_trace_id = cs_trace_id; cs->cst->cs_trace_id = cs_trace_id;
/* If the CS is not empty or overflowed, emit it in a separate thread. */ /* If the CS is not empty or overflowed, emit it in a separate thread. */
if (cs->base.cdw && cs->base.cdw <= RADEON_MAX_CMDBUF_DWORDS && !debug_get_option_noop()) { if (cs->base.cdw && cs->base.cdw <= cs->base.max_dw && !debug_get_option_noop()) {
unsigned i, crelocs; unsigned i, crelocs;
crelocs = cs->cst->crelocs; crelocs = cs->cst->crelocs;

2
src/gallium/winsys/radeon/drm/radeon_drm_cs.h
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@@ -30,7 +30,7 @@
#include "radeon_drm_bo.h" #include "radeon_drm_bo.h"
struct radeon_cs_context { struct radeon_cs_context {
uint32_t buf[RADEON_MAX_CMDBUF_DWORDS]; uint32_t buf[16 * 1024];
int fd; int fd;
struct drm_radeon_cs cs; struct drm_radeon_cs cs;