From d559764e7ccb6b78f7ebb738301dedc712f97243 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 1 Aug 2023 11:05:53 -0400 Subject: [PATCH] nir: Remove nir_alu_dest::saturate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Alyssa Rosenzweig Reviewed-by: Faith Ekstrand Reviewed-by: Marek Olšák Part-of: --- src/broadcom/compiler/nir_to_vir.c | 3 --- src/compiler/nir/nir.c | 7 ++----- src/compiler/nir/nir.h | 8 -------- src/compiler/nir/nir_clone.c | 1 - src/compiler/nir/nir_loop_analyze.c | 3 --- src/compiler/nir/nir_lower_alu_width.c | 1 - src/compiler/nir/nir_move_vec_src_uses_to_dest.c | 4 ---- src/compiler/nir/nir_opt_comparison_pre.c | 3 --- src/compiler/nir/nir_opt_constant_folding.c | 3 --- src/compiler/nir/nir_opt_if.c | 1 - src/compiler/nir/nir_opt_peephole_select.c | 4 ---- src/compiler/nir/nir_print.c | 2 -- src/compiler/nir/nir_search.c | 2 -- src/compiler/nir/nir_serialize.c | 4 +--- src/compiler/nir/nir_validate.c | 13 ------------- .../drivers/etnaviv/etnaviv_nir_lower_source_mods.c | 3 --- src/gallium/drivers/vc4/vc4_program.c | 3 --- .../drivers/zink/nir_to_spirv/nir_to_spirv.c | 1 - src/intel/compiler/brw_fs_nir.cpp | 2 -- src/intel/compiler/brw_nir_opt_peephole_ffma.c | 1 - src/intel/compiler/brw_nir_opt_peephole_imul32x16.c | 1 - src/intel/compiler/brw_vec4_nir.cpp | 2 -- src/microsoft/compiler/nir_to_dxil.c | 1 - src/nouveau/codegen/nv50_ir_from_nir.cpp | 1 - 24 files changed, 3 insertions(+), 71 deletions(-) diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c index 3ccc0d5acbe..9c5ad2aad43 100644 --- a/src/broadcom/compiler/nir_to_vir.c +++ b/src/broadcom/compiler/nir_to_vir.c @@ -1356,9 +1356,6 @@ sign_extend(struct v3d_compile *c, static void ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) { - /* This should always be lowered to ALU operations for V3D. */ - assert(!instr->dest.saturate); - /* Vectors are special in that they have non-scalarized writemasks, * and just take the first swizzle channel for each argument in order * into each writemask channel. diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c index 09830bd6ec8..7166b30c4b0 100644 --- a/src/compiler/nir/nir.c +++ b/src/compiler/nir/nir.c @@ -530,7 +530,6 @@ nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src, { nir_dest_copy(&dest->dest, &src->dest, &instr->instr); dest->write_mask = src->write_mask; - dest->saturate = src->saturate; } bool @@ -693,7 +692,6 @@ static void alu_dest_init(nir_alu_dest *dest) { dest_init(&dest->dest); - dest->saturate = false; dest->write_mask = 0xf; } @@ -2919,15 +2917,14 @@ nir_alu_instr_is_copy(nir_alu_instr *instr) assert(instr->src[0].src.is_ssa); if (instr->op == nir_op_mov) { - return !instr->dest.saturate && - !instr->src[0].abs && + return !instr->src[0].abs && !instr->src[0].negate; } else if (nir_op_is_vec(instr->op)) { for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; i++) { if (instr->src[i].abs || instr->src[i].negate) return false; } - return !instr->dest.saturate; + return true; } else { return false; } diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index db9bfe2e25c..c16634674cd 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1219,14 +1219,6 @@ typedef struct { /** Base destination */ nir_dest dest; - /** - * Saturate output modifier - * - * Only valid for opcodes that output floating-point numbers. Clamps the - * output to between 0.0 and 1.0 inclusive. - */ - bool saturate; - /** * Write-mask * diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c index 30fc5e8d011..ffbae1863ba 100644 --- a/src/compiler/nir/nir_clone.c +++ b/src/compiler/nir/nir_clone.c @@ -225,7 +225,6 @@ clone_alu(clone_state *state, const nir_alu_instr *alu) nalu->no_unsigned_wrap = alu->no_unsigned_wrap; __clone_dst(state, &nalu->instr, &nalu->dest.dest, &alu->dest.dest); - nalu->dest.saturate = alu->dest.saturate; nalu->dest.write_mask = alu->dest.write_mask; for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { diff --git a/src/compiler/nir/nir_loop_analyze.c b/src/compiler/nir/nir_loop_analyze.c index 376b4097cae..8651b46a40c 100644 --- a/src/compiler/nir/nir_loop_analyze.c +++ b/src/compiler/nir/nir_loop_analyze.c @@ -824,9 +824,6 @@ try_eval_const_alu(nir_const_value *dest, nir_alu_instr *alu, if (bit_size == 0) bit_size = 32; - /* We shouldn't have any saturate modifiers in the optimization loop. */ - assert(!alu->dest.saturate); - nir_const_value *srcs[NIR_MAX_VEC_COMPONENTS]; for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; ++i) diff --git a/src/compiler/nir/nir_lower_alu_width.c b/src/compiler/nir/nir_lower_alu_width.c index 41c3bfcb24f..f2872f0a87b 100644 --- a/src/compiler/nir/nir_lower_alu_width.c +++ b/src/compiler/nir/nir_lower_alu_width.c @@ -415,7 +415,6 @@ lower_alu_instr_width(nir_builder *b, nir_instr *instr, void *_data) } nir_alu_ssa_dest_init(lower, components, alu->dest.dest.ssa.bit_size); - lower->dest.saturate = alu->dest.saturate; lower->exact = alu->exact; for (i = 0; i < components; i++) { diff --git a/src/compiler/nir/nir_move_vec_src_uses_to_dest.c b/src/compiler/nir/nir_move_vec_src_uses_to_dest.c index 945e7560671..c46035c54dc 100644 --- a/src/compiler/nir/nir_move_vec_src_uses_to_dest.c +++ b/src/compiler/nir/nir_move_vec_src_uses_to_dest.c @@ -81,10 +81,6 @@ move_vec_src_uses_to_dest_block(nir_block *block) if (!vec->dest.dest.is_ssa) continue; - /* Can't handle saturation */ - if (vec->dest.saturate) - continue; - /* First, mark all of the sources we are going to consider for rewriting * to the destination */ diff --git a/src/compiler/nir/nir_opt_comparison_pre.c b/src/compiler/nir/nir_opt_comparison_pre.c index 5c66039c792..ba089de7577 100644 --- a/src/compiler/nir/nir_opt_comparison_pre.c +++ b/src/compiler/nir/nir_opt_comparison_pre.c @@ -258,9 +258,6 @@ comparison_pre_block(nir_block *block, struct block_queue *bq, nir_builder *bld) if (alu->dest.dest.ssa.num_components != 1) continue; - if (alu->dest.saturate) - continue; - static const uint8_t swizzle[NIR_MAX_VEC_COMPONENTS] = {0}; switch (alu->op) { diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index 945055f5451..29e2dde6aee 100644 --- a/src/compiler/nir/nir_opt_constant_folding.c +++ b/src/compiler/nir/nir_opt_constant_folding.c @@ -83,9 +83,6 @@ try_fold_alu(nir_builder *b, nir_alu_instr *alu) if (bit_size == 0) bit_size = 32; - /* We shouldn't have any saturate modifiers in the optimization loop. */ - assert(!alu->dest.saturate); - nir_const_value dest[NIR_MAX_VEC_COMPONENTS]; nir_const_value *srcs[NIR_MAX_VEC_COMPONENTS]; memset(dest, 0, sizeof(dest)); diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c index 854ecba6207..0aef197d4af 100644 --- a/src/compiler/nir/nir_opt_if.c +++ b/src/compiler/nir/nir_opt_if.c @@ -1187,7 +1187,6 @@ clone_alu_and_replace_src_defs(nir_builder *b, const nir_alu_instr *alu, alu->dest.dest.ssa.num_components, alu->dest.dest.ssa.bit_size); - nalu->dest.saturate = alu->dest.saturate; nalu->dest.write_mask = alu->dest.write_mask; for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c index 288ec6aaa4f..d173dd884ee 100644 --- a/src/compiler/nir/nir_opt_peephole_select.c +++ b/src/compiler/nir/nir_opt_peephole_select.c @@ -225,10 +225,6 @@ block_check_for_allowed_instrs(nir_block *block, unsigned *count, if (mov->op != nir_op_fsat && !movelike) (*count)++; } else { - /* Can't handle saturate */ - if (mov->dest.saturate) - return false; - /* The only uses of this definition must be phis in the successor */ nir_foreach_use_including_if(use, &mov->dest.dest.ssa) { if (use->is_if || diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index 908bba29791..6a9c608b3b2 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -455,8 +455,6 @@ print_alu_instr(nir_alu_instr *instr, print_state *state) fprintf(fp, " = %s", nir_op_infos[instr->op].name); if (instr->exact) fprintf(fp, "!"); - if (instr->dest.saturate) - fprintf(fp, ".sat"); if (instr->no_signed_wrap) fprintf(fp, ".nsw"); if (instr->no_unsigned_wrap) diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c index 5a32057c17a..23ce9065f69 100644 --- a/src/compiler/nir/nir_search.c +++ b/src/compiler/nir/nir_search.c @@ -381,7 +381,6 @@ match_expression(const nir_algebraic_table *table, const nir_search_expression * if (state->inexact_match && state->has_exact_alu) return false; - assert(!instr->dest.saturate); assert(nir_op_infos[instr->op].num_inputs > 0); /* If we have an explicitly sized destination, we can only handle the @@ -453,7 +452,6 @@ construct_value(nir_builder *build, nir_ssa_dest_init(&alu->instr, &alu->dest.dest, num_components, dst_bit_size); alu->dest.write_mask = (1 << num_components) - 1; - alu->dest.saturate = false; /* We have no way of knowing what values in a given search expression * map to a particular replacement value. Therefore, if the diff --git a/src/compiler/nir/nir_serialize.c b/src/compiler/nir/nir_serialize.c index 4974ef25dd0..2bd34c50095 100644 --- a/src/compiler/nir/nir_serialize.c +++ b/src/compiler/nir/nir_serialize.c @@ -542,7 +542,7 @@ union packed_instr { unsigned exact:1; unsigned no_signed_wrap:1; unsigned no_unsigned_wrap:1; - unsigned saturate:1; + unsigned padding:1; /* Reg: writemask; SSA: swizzles for 2 srcs */ unsigned writemask_or_two_swizzles:4; unsigned op:9; @@ -731,7 +731,6 @@ write_alu(write_ctx *ctx, const nir_alu_instr *alu) header.alu.exact = alu->exact; header.alu.no_signed_wrap = alu->no_signed_wrap; header.alu.no_unsigned_wrap = alu->no_unsigned_wrap; - header.alu.saturate = alu->dest.saturate; header.alu.op = alu->op; header.alu.packed_src_ssa_16bit = is_alu_src_ssa_16bit(ctx, alu); @@ -796,7 +795,6 @@ read_alu(read_ctx *ctx, union packed_instr header) alu->exact = header.alu.exact; alu->no_signed_wrap = header.alu.no_signed_wrap; alu->no_unsigned_wrap = header.alu.no_unsigned_wrap; - alu->dest.saturate = header.alu.saturate; read_dest(ctx, &alu->dest.dest, &alu->instr, header); diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c index f682d1f3737..374349a1f55 100644 --- a/src/compiler/nir/nir_validate.c +++ b/src/compiler/nir/nir_validate.c @@ -222,10 +222,6 @@ static void validate_alu_dest(nir_alu_instr *instr, validate_state *state) { nir_alu_dest *dest = &instr->dest; - - if (instr->op == nir_op_mov) - assert(!dest->saturate); - unsigned dest_size = nir_dest_num_components(dest->dest); /* * validate that the instruction doesn't write to components not in the @@ -233,15 +229,6 @@ validate_alu_dest(nir_alu_instr *instr, validate_state *state) */ validate_assert(state, !(dest->write_mask & ~nir_component_mask(dest_size))); - /* validate that saturate is only ever used on instructions with - * destinations of type float - */ - nir_alu_instr *alu = nir_instr_as_alu(state->instr); - validate_assert(state, - (nir_alu_type_get_base_type(nir_op_infos[alu->op].output_type) == - nir_type_float) || - !dest->saturate); - validate_dest(&dest->dest, state, 0, 0); } diff --git a/src/gallium/drivers/etnaviv/etnaviv_nir_lower_source_mods.c b/src/gallium/drivers/etnaviv/etnaviv_nir_lower_source_mods.c index 1d22bf7a969..702d0b4907c 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_nir_lower_source_mods.c +++ b/src/gallium/drivers/etnaviv/etnaviv_nir_lower_source_mods.c @@ -64,9 +64,6 @@ nir_lower_to_source_mods_instr(nir_builder *b, nir_instr *instr, nir_alu_instr *parent = nir_instr_as_alu(alu->src[i].src.ssa->parent_instr); - if (parent->dest.saturate) - continue; - if (nir_alu_type_get_base_type(nir_op_infos[alu->op].input_types[i]) != nir_type_float) continue; diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c index 7485f973c88..1881512f851 100644 --- a/src/gallium/drivers/vc4/vc4_program.c +++ b/src/gallium/drivers/vc4/vc4_program.c @@ -1067,9 +1067,6 @@ ntq_emit_cond_to_int(struct vc4_compile *c, enum qpu_cond cond) static void ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr) { - /* This should always be lowered to ALU operations for VC4. */ - assert(!instr->dest.saturate); - /* Vectors are special in that they have non-scalarized writemasks, * and just take the first swizzle channel for each argument in order * into each writemask channel. diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index 5755e6bef0c..b02d19ef18e 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -2072,7 +2072,6 @@ get_alu_src(struct ntv_context *ctx, nir_alu_instr *alu, unsigned src, SpvId *ra static void store_alu_result(struct ntv_context *ctx, nir_alu_instr *alu, SpvId result, nir_alu_type atype) { - assert(!alu->dest.saturate); store_dest(ctx, &alu->dest.dest, result, atype); } diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index b7505d8b4de..8a0cee85233 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -647,8 +647,6 @@ fs_visitor::prepare_alu_destination_and_sources(const fs_builder &bld, (nir_alu_type)(nir_op_infos[instr->op].output_type | nir_dest_bit_size(instr->dest.dest))); - assert(!instr->dest.saturate); - for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { /* We don't lower to source modifiers so they should not exist. */ assert(!instr->src[i].abs); diff --git a/src/intel/compiler/brw_nir_opt_peephole_ffma.c b/src/intel/compiler/brw_nir_opt_peephole_ffma.c index b01fe51a59c..2ef6800f2f1 100644 --- a/src/intel/compiler/brw_nir_opt_peephole_ffma.c +++ b/src/intel/compiler/brw_nir_opt_peephole_ffma.c @@ -228,7 +228,6 @@ brw_nir_opt_peephole_ffma_instr(nir_builder *b, mul_src[0] = nir_fneg(b, mul_src[0]); nir_alu_instr *ffma = nir_alu_instr_create(b->shader, nir_op_ffma); - ffma->dest.saturate = add->dest.saturate; ffma->dest.write_mask = add->dest.write_mask; for (unsigned i = 0; i < 2; i++) { diff --git a/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c b/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c index 859ab968bfa..06ee5a06490 100644 --- a/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c +++ b/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c @@ -41,7 +41,6 @@ replace_imul_instr(nir_builder *b, nir_alu_instr *imul, unsigned small_val, b->cursor = nir_before_instr(&imul->instr); nir_alu_instr *imul_32x16 = nir_alu_instr_create(b->shader, new_opcode); - imul_32x16->dest.saturate = imul->dest.saturate; imul_32x16->dest.write_mask = imul->dest.write_mask; nir_alu_src_copy(&imul_32x16->src[0], &imul->src[1 - small_val], imul_32x16); diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 5bc0440dedc..4fec7cb9865 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -1089,8 +1089,6 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) dst_reg dst = get_nir_dest(instr->dest.dest, dst_type); dst.writemask &= instr->dest.write_mask; - assert(!instr->dest.saturate); - src_reg op[4]; for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { /* We don't lower to source modifiers, so they shouldn't exist. */ diff --git a/src/microsoft/compiler/nir_to_dxil.c b/src/microsoft/compiler/nir_to_dxil.c index 68021c9b6c1..46b96a88a3a 100644 --- a/src/microsoft/compiler/nir_to_dxil.c +++ b/src/microsoft/compiler/nir_to_dxil.c @@ -2185,7 +2185,6 @@ static void store_alu_dest(struct ntd_context *ctx, nir_alu_instr *alu, unsigned chan, const struct dxil_value *value) { - assert(!alu->dest.saturate); store_dest(ctx, &alu->dest.dest, chan, value); } diff --git a/src/nouveau/codegen/nv50_ir_from_nir.cpp b/src/nouveau/codegen/nv50_ir_from_nir.cpp index 83863e6cc76..c32739e4081 100644 --- a/src/nouveau/codegen/nv50_ir_from_nir.cpp +++ b/src/nouveau/codegen/nv50_ir_from_nir.cpp @@ -2911,7 +2911,6 @@ Converter::visit(nir_alu_instr *insn) oldPos = oldPos->next; oldPos->precise = insn->exact; } - oldPos->saturate = insn->dest.saturate; return true; }