From d52dd5a9e954bcf9571cd1547f17f870264820bb Mon Sep 17 00:00:00 2001 From: Sushma Venkatesh Reddy Date: Fri, 28 Jun 2024 10:09:53 -0700 Subject: [PATCH] anv/drirc: add option to provide low latency hint MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GuC offers a mechanism for KMD/UMD to provide workload hints and one of that strategy is low latency hint. We can utilize this hint when the workload is more latency sensitive like compute usecases. Signed-off-by: Sushma Venkatesh Reddy Reviewed-by: José Roberto de Souza Part-of: --- src/intel/common/i915/intel_gem.c | 12 ++++++++++++ src/intel/common/intel_gem.h | 1 + src/intel/vulkan/anv_device.c | 2 ++ src/intel/vulkan/anv_private.h | 1 + src/intel/vulkan/i915/anv_queue.c | 7 +++++++ src/util/driconf.h | 4 ++++ 6 files changed, 27 insertions(+) diff --git a/src/intel/common/i915/intel_gem.c b/src/intel/common/i915/intel_gem.c index 5d8525d73ff..037d7d8dd66 100644 --- a/src/intel/common/i915/intel_gem.c +++ b/src/intel/common/i915/intel_gem.c @@ -135,6 +135,12 @@ i915_gem_create_context_engines(int fd, .value = flags & INTEL_GEM_CREATE_CONTEXT_EXT_RECOVERABLE_FLAG, }, }; + struct drm_i915_gem_context_create_ext_setparam low_latency_param = { + .param = { + .param = I915_CONTEXT_PARAM_LOW_LATENCY, + .value = flags & INTEL_GEM_CREATE_CONTEXT_EXT_LOW_LATENCY_FLAG, + } + }; struct drm_i915_gem_context_create_ext create = { .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, }; @@ -164,6 +170,12 @@ i915_gem_create_context_engines(int fd, &protected_param.base); } + if (flags & INTEL_GEM_CREATE_CONTEXT_EXT_LOW_LATENCY_FLAG) { + intel_i915_gem_add_ext(&create.extensions, + I915_CONTEXT_CREATE_EXT_SETPARAM, + &low_latency_param.base); + } + if (intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create) == -1) return false; diff --git a/src/intel/common/intel_gem.h b/src/intel/common/intel_gem.h index bb773888c38..1fd3ba82d6f 100644 --- a/src/intel/common/intel_gem.h +++ b/src/intel/common/intel_gem.h @@ -105,6 +105,7 @@ bool intel_gem_can_render_on_fd(int fd, enum intel_kmd_type kmd_type); enum intel_gem_create_context_flags { INTEL_GEM_CREATE_CONTEXT_EXT_RECOVERABLE_FLAG = BITFIELD_BIT(0), INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG = BITFIELD_BIT(1), + INTEL_GEM_CREATE_CONTEXT_EXT_LOW_LATENCY_FLAG = BITFIELD_BIT(2), }; bool intel_gem_create_context(int fd, uint32_t *context_id); diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 4f5e2e56a79..109c825eaed 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -81,6 +81,7 @@ static const driOptionDescription anv_dri_options[] = { DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS(0) DRI_CONF_ANV_DISABLE_FCV(false) DRI_CONF_ANV_EXTERNAL_MEMORY_IMPLICIT_SYNC(true) + DRI_CONF_ANV_FORCE_GUC_LOW_LATENCY(false) DRI_CONF_ANV_SAMPLE_MASK_OUT_OPENGL_BEHAVIOUR(false) DRI_CONF_ANV_FORCE_FILTER_ADDR_ROUNDING(false) DRI_CONF_ANV_FP64_WORKAROUND_ENABLED(false) @@ -2734,6 +2735,7 @@ anv_init_dri_options(struct anv_instance *instance) instance->stack_ids = 512; break; } + instance->force_guc_low_latency = driQueryOptionb(&instance->dri_options, "force_guc_low_latency"); } VkResult anv_CreateInstance( diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index f80f4db9fa6..24a25127970 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1265,6 +1265,7 @@ struct anv_instance { int mesh_conv_prim_attrs_to_vert_attrs; bool enable_tbimr; bool external_memory_implicit_sync; + bool force_guc_low_latency; /** * Workarounds for game bugs. diff --git a/src/intel/vulkan/i915/anv_queue.c b/src/intel/vulkan/i915/anv_queue.c index 173cf7b2a3a..d1406c744f3 100644 --- a/src/intel/vulkan/i915/anv_queue.c +++ b/src/intel/vulkan/i915/anv_queue.c @@ -25,6 +25,7 @@ #include "anv_private.h" #include "common/i915/intel_engine.h" +#include "common/i915/intel_gem.h" #include "common/intel_gem.h" #include "i915/anv_device.h" @@ -59,11 +60,17 @@ anv_i915_create_engine(struct anv_device *device, assert(pCreateInfo->queueFamilyIndex < physical->queue.family_count); enum intel_engine_class engine_classes[1]; enum intel_gem_create_context_flags flags = 0; + int val = 0; engine_classes[0] = queue_family->engine_class; if (pCreateInfo->flags & VK_DEVICE_QUEUE_CREATE_PROTECTED_BIT) flags |= INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG; + if (device->physical->instance->force_guc_low_latency && + i915_gem_get_param(device->fd, I915_PARAM_HAS_CONTEXT_FREQ_HINT, &val) && val) { + flags |= INTEL_GEM_CREATE_CONTEXT_EXT_LOW_LATENCY_FLAG; + } + if (!intel_gem_create_context_engines(device->fd, flags, physical->engine_info, 1, engine_classes, diff --git a/src/util/driconf.h b/src/util/driconf.h index b9cb8351505..70f82e82dbb 100644 --- a/src/util/driconf.h +++ b/src/util/driconf.h @@ -802,6 +802,10 @@ DRI_CONF_OPT_B(hasvk_report_vk_1_3_version, def, \ "Override intel_hasvk API version") +#define DRI_CONF_ANV_FORCE_GUC_LOW_LATENCY(def) \ + DRI_CONF_OPT_B(force_guc_low_latency, def, \ + "Enable low latency GuC strategy. Only supported on i915.") + /** * \brief DZN specific configuration options */