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intel: add missing restriction on fragment simd dispatch

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7755
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20169>
This commit is contained in:
Lionel Landwerlin
2022-12-05 20:27:59 +02:00
parent b9403b1c47
commit d4cd33630a
1 changed files with 8 additions and 0 deletions
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8
src/intel/compiler/brw_compiler.h
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@@ -999,6 +999,14 @@ brw_fs_get_dispatch_enables(const struct intel_device_info *devinfo,
*enable_32 = prog_data->dispatch_32;
if (prog_data->persample_dispatch) {
/* TGL PRMs, Volume 2d: Command Reference: Structures:
* 3DSTATE_PS_BODY::32 Pixel Dispatch Enable:
*
* "Must not be enabled when dispatch rate is sample AND NUM_MULTISAMPLES > 1."
*/
if (devinfo->ver >= 12 && rasterization_samples > 1)
*enable_32 = false;
/* Starting with SandyBridge (where we first get MSAA), the different
* pixel dispatch combinations are grouped into classifications A
* through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On most hardware