freedreno/a3xx/compiler: add TGSI_OPCODE_ABS
Signed-off-by: Rob Clark <robclark@freedesktop.org>
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@@ -940,12 +940,19 @@ instr_cat2(const struct instr_translater *t,
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{
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struct tgsi_dst_register *dst = get_dst(ctx, inst);
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struct ir3_instruction *instr;
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assert(inst->Instruction.NumSrcRegs == 2);
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assert(inst->Instruction.NumDstRegs == 1);
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unsigned src0_flags = 0;
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instr = ir3_instr_create(ctx->ir, 2, t->opc);
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instr->cat2.condition = t->arg;
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switch (t->tgsi_opc) {
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case TGSI_OPCODE_SLT:
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case TGSI_OPCODE_SGE:
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instr->cat2.condition = t->arg;
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break;
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case TGSI_OPCODE_ABS:
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src0_flags = IR3_REG_ABS;
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break;
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}
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switch (t->opc) {
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case OPC_ABSNEG_F:
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@@ -964,11 +971,11 @@ instr_cat2(const struct instr_translater *t,
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case OPC_CBITS_B:
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/* these only have one src reg */
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vectorize(ctx, instr, dst, 1,
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&inst->Src[0].Register, 0);
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&inst->Src[0].Register, src0_flags);
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break;
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default:
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vectorize(ctx, instr, dst, 2,
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&inst->Src[0].Register, 0,
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&inst->Src[0].Register, src0_flags,
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&inst->Src[1].Register, 0);
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break;
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}
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@@ -1053,6 +1060,7 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
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INSTR(EX2, instr_cat4, .opc = OPC_EXP2),
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INSTR(LG2, instr_cat4, .opc = OPC_LOG2),
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INSTR(POW, trans_pow),
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INSTR(ABS, instr_cat2, .opc = OPC_ABSNEG_F),
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INSTR(COS, instr_cat4, .opc = OPC_SIN),
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INSTR(SIN, instr_cat4, .opc = OPC_COS),
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INSTR(TEX, trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TEX),
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