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iris: Implement INTEL_DEBUG=pc for pipe control logging.

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This prints a log of every PIPE_CONTROL flush we emit, noting which bits
were set, and also the reason for the flush.  That way we can see which
are caused by hardware workarounds, render-to-texture, buffer updates,
and so on.  It should make it easier to determine whether we're doing
too many flushes and why.
This commit is contained in:
Kenneth Graunke
2019-06-19 16:04:50 -05:00
parent c378829a0d
commit d4a4384b31
13 changed files with 170 additions and 57 deletions
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14
src/gallium/drivers/iris/iris_blit.c
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@@ -289,8 +289,12 @@ tex_cache_flush_hack(struct iris_batch *batch)
*
* TODO: Remove this hack!
*/
iris_emit_pipe_control_flush(batch, PIPE_CONTROL_CS_STALL);
iris_emit_pipe_control_flush(batch, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
const char *reason =
"workaround: WaSamplerCacheFlushBetweenRedescribedSurfaceReads";
iris_emit_pipe_control_flush(batch, reason, PIPE_CONTROL_CS_STALL);
iris_emit_pipe_control_flush(batch, reason,
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
}
/**
@@ -488,7 +492,8 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
info->dst.box.depth, dst_aux_usage);
iris_flush_and_dirty_for_history(ice, batch, (struct iris_resource *)
info->dst.resource);
info->dst.resource,
"cache history: post-blit");
}
static void
@@ -569,7 +574,8 @@ iris_copy_region(struct blorp_context *blorp,
blorp_batch_finish(&blorp_batch);
iris_flush_and_dirty_for_history(ice, batch,
(struct iris_resource *) dst);
(struct iris_resource *) dst,
"cache history: post copy_region");
} else {
// XXX: what about one surface being a buffer and not the other?