intel/compiler: Move base IR definitions into a separate header file
This pulls out the i965 IR definitions into a separate file and leaves
the top-level backend_shader structure and back-end compiler entry
points in brw_shader.h. The purpose is to keep things tidy and
prevent a nasty circular dependency between brw_cfg.h and
brw_shader.h. The logical dependency between these data structures
looks like:
backend_shader (brw_shader.h) -> cfg_t (brw_cfg.h)
-> bblock_t (brw_cfg.h) -> backend_instruction (brw_shader.h)
This circular header dependency is currently resolved by using forward
declarations of cfg_t/bblock_t in brw_shader.h and having brw_cfg.h
include brw_shader.h, which seems backwards and won't work at all when
the forward declarations of cfg_t/bblock_t are no longer sufficient in
a future commit.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
This commit is contained in:
Francisco Jerez
committed by
Matt Turner
Matt Turner
parent
74e4cda64b
commit
d46fb2126d
181
src/intel/compiler/brw_ir.h
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181
src/intel/compiler/brw_ir.h
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/* -*- c++ -*- */
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/*
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* Copyright © 2010-2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef BRW_IR_H
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#define BRW_IR_H
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#include <assert.h>
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#include "brw_reg.h"
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#include "compiler/glsl/list.h"
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#define MAX_SAMPLER_MESSAGE_SIZE 11
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#define MAX_VGRF_SIZE 16
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#ifdef __cplusplus
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struct backend_reg : private brw_reg
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{
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backend_reg() {}
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backend_reg(const struct brw_reg ®) : brw_reg(reg) {}
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const brw_reg &as_brw_reg() const
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{
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assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
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assert(offset == 0);
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return static_cast<const brw_reg &>(*this);
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}
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brw_reg &as_brw_reg()
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{
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assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
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assert(offset == 0);
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return static_cast<brw_reg &>(*this);
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}
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bool equals(const backend_reg &r) const;
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bool negative_equals(const backend_reg &r) const;
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bool is_zero() const;
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bool is_one() const;
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bool is_negative_one() const;
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bool is_null() const;
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bool is_accumulator() const;
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/** Offset from the start of the (virtual) register in bytes. */
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uint16_t offset;
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using brw_reg::type;
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using brw_reg::file;
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using brw_reg::negate;
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using brw_reg::abs;
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using brw_reg::address_mode;
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using brw_reg::subnr;
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using brw_reg::nr;
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using brw_reg::swizzle;
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using brw_reg::writemask;
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using brw_reg::indirect_offset;
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using brw_reg::vstride;
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using brw_reg::width;
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using brw_reg::hstride;
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using brw_reg::df;
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using brw_reg::f;
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using brw_reg::d;
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using brw_reg::ud;
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using brw_reg::d64;
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using brw_reg::u64;
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};
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struct bblock_t;
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struct backend_instruction : public exec_node {
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bool is_3src(const struct gen_device_info *devinfo) const;
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bool is_tex() const;
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bool is_math() const;
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bool is_control_flow() const;
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bool is_commutative() const;
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bool can_do_source_mods() const;
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bool can_do_saturate() const;
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bool can_do_cmod() const;
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bool reads_accumulator_implicitly() const;
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bool writes_accumulator_implicitly(const struct gen_device_info *devinfo) const;
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void remove(bblock_t *block);
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void insert_after(bblock_t *block, backend_instruction *inst);
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void insert_before(bblock_t *block, backend_instruction *inst);
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void insert_before(bblock_t *block, exec_list *list);
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/**
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* True if the instruction has side effects other than writing to
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* its destination registers. You are expected not to reorder or
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* optimize these out unless you know what you are doing.
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*/
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bool has_side_effects() const;
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/**
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* True if the instruction might be affected by side effects of other
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* instructions.
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*/
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bool is_volatile() const;
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#else
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struct backend_instruction {
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struct exec_node link;
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#endif
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/** @{
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* Annotation for the generated IR. One of the two can be set.
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*/
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const void *ir;
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const char *annotation;
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/** @} */
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/**
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* Execution size of the instruction. This is used by the generator to
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* generate the correct binary for the given instruction. Current valid
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* values are 1, 4, 8, 16, 32.
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*/
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uint8_t exec_size;
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/**
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* Channel group from the hardware execution and predication mask that
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* should be applied to the instruction. The subset of channel enable
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* signals (calculated from the EU control flow and predication state)
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* given by [group, group + exec_size) will be used to mask GRF writes and
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* any other side effects of the instruction.
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*/
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uint8_t group;
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uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
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uint8_t mlen; /**< SEND message length */
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uint8_t ex_mlen; /**< SENDS extended message length */
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int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
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uint8_t target; /**< MRT target. */
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uint8_t sfid; /**< SFID for SEND instructions */
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uint32_t desc; /**< SEND[S] message descriptor immediate */
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unsigned size_written; /**< Data written to the destination register in bytes. */
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enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
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enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
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enum brw_predicate predicate;
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bool predicate_inverse:1;
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bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
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bool force_writemask_all:1;
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bool no_dd_clear:1;
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bool no_dd_check:1;
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bool saturate:1;
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bool shadow_compare:1;
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bool check_tdr:1; /**< Only valid for SEND; turns it into a SENDC */
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bool send_has_side_effects:1; /**< Only valid for SHADER_OPCODE_SEND */
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bool send_is_volatile:1; /**< Only valid for SHADER_OPCODE_SEND */
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bool eot:1;
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/* Chooses which flag subregister (f0.0 to f1.1) is used for conditional
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* mod and predication.
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*/
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unsigned flag_subreg:2;
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/** The number of hardware registers used for a message header. */
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uint8_t header_size;
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};
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#endif
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