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i965: Use UW-typed immediate in multiply inst.

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Some hardware reads only the low 16-bits even if the type is UD, but
other hardware like Cherryview can't handle this.

Fixes spec@arb_gpu_shader5@execution@sampler_array_indexing@fs-simple on
Cherryview.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90830
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
This commit is contained in:
Matt Turner
2015-06-02 17:46:38 -07:00
parent 54a70a8ef2
commit d46d04529b
2 changed files with 2 additions and 2 deletions
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2
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View File

@@ -788,7 +788,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
brw_set_default_access_mode(p, BRW_ALIGN_1);
/* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
brw_MUL(p, addr, sampler_reg, brw_imm_ud(0x101));
brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
if (base_binding_table_index)
brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
brw_AND(p, addr, addr, brw_imm_ud(0xfff));

2
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View File

@@ -407,7 +407,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
brw_set_default_access_mode(p, BRW_ALIGN_1);
/* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
brw_MUL(p, addr, sampler_reg, brw_imm_ud(0x101));
brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
if (base_binding_table_index)
brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
brw_AND(p, addr, addr, brw_imm_ud(0xfff));