From d3e5e04a75e90bd321ae6e2b840fc46d08fd666a Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Mon, 19 Jun 2023 13:00:19 +0100 Subject: [PATCH] amd/drm-shim: use fixed-width types Signed-off-by: Rhys Perry Reviewed-by: Eric Engestrom Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9221 Part-of: --- src/amd/drm-shim/amdgpu_devices.c | 670 +++++++++++++------------- src/amd/drm-shim/amdgpu_dump_states.c | 62 +-- 2 files changed, 369 insertions(+), 363 deletions(-) diff --git a/src/amd/drm-shim/amdgpu_devices.c b/src/amd/drm-shim/amdgpu_devices.c index c99bddfb89d..3c8328aa686 100644 --- a/src/amd/drm-shim/amdgpu_devices.c +++ b/src/amd/drm-shim/amdgpu_devices.c @@ -58,7 +58,7 @@ const struct amdgpu_device amdgpu_devices[] = { .num_hw_gfx_contexts = 8, .ids_flags = 0x5, .virtual_address_offset = 0x200000, - .virtual_address_max = 0x800000000000llu, + .virtual_address_max = UINT64_C(0x800000000000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -74,18 +74,18 @@ const struct amdgpu_device amdgpu_devices[] = { .gs_prim_buffer_depth = 1792, .max_gs_waves_per_vgt = 32, .cu_ao_bitmap[0][0] = 0xfe, - .high_va_offset = 0xffff800000000000llu, - .high_va_max = 0xffffffffffe00000llu, + .high_va_offset = UINT64_C(0xffff800000000000), + .high_va_max = UINT64_C(0xffffffffffe00000), }, .mem = { .vram = { - .total_heap_size = 64ull << 20, + .total_heap_size = UINT64_C(64) << 20, }, .cpu_accessible_vram = { - .total_heap_size = 64ull << 20, + .total_heap_size = UINT64_C(64) << 20, }, .gtt = { - .total_heap_size = 4096ull << 20, + .total_heap_size = UINT64_C(4096) << 20, }, }, }, @@ -139,7 +139,7 @@ const struct amdgpu_device amdgpu_devices[] = { .num_hw_gfx_contexts = 8, .ids_flags = 0x1, .virtual_address_offset = 0x200000, - .virtual_address_max = 0x800000000000llu, + .virtual_address_max = UINT64_C(0x800000000000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -155,18 +155,18 @@ const struct amdgpu_device amdgpu_devices[] = { .gs_prim_buffer_depth = 1792, .max_gs_waves_per_vgt = 32, .cu_ao_bitmap[0][0] = 0x3ff, - .high_va_offset = 0xffff800000000000llu, - .high_va_max = 0xffffffffffe00000llu, + .high_va_offset = UINT64_C(0xffff800000000000), + .high_va_max = UINT64_C(0xffffffffffe00000), }, .mem = { .vram = { - .total_heap_size = 64ull << 20, + .total_heap_size = UINT64_C(64) << 20, }, .cpu_accessible_vram = { - .total_heap_size = 64ull << 20, + .total_heap_size = UINT64_C(64) << 20, }, .gtt = { - .total_heap_size = 3072ull << 20, + .total_heap_size = UINT64_C(3072) << 20, }, }, }, @@ -176,7 +176,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 9, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -185,7 +185,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 9, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0xf, @@ -216,8 +216,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 1, .num_shader_arrays_per_engine = 1, .gpu_counter_freq = 100000, - .max_engine_clock = 600000llu, - .max_memory_clock = 800000llu, + .max_engine_clock = UINT64_C(600000), + .max_memory_clock = UINT64_C(800000), .cu_active_number = 3, .cu_ao_mask = 0x7, .cu_bitmap = { @@ -230,9 +230,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 1, .num_hw_gfx_contexts = 8, .pcie_gen = 0, - .ids_flags = 0x1llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0x800000000000llu, + .ids_flags = UINT64_C(0x1), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0x800000000000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -241,10 +241,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 64, .vce_harvest_config = 0, .gc_double_offchip_lds_buf = 1, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -263,39 +263,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0x0, 0x0, 0x0, 0x0, }, { 0x0, 0x0, 0x0, 0x0, }, }, - .high_va_offset = 0xffff800000000000llu, - .high_va_max = 0xffffffffffe00000llu, + .high_va_offset = UINT64_C(0xffff800000000000), + .high_va_max = UINT64_C(0xffffffffffe00000), .pa_sc_tile_steering_override = 0, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 0llu, - .min_memory_clock = 0llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(0), + .min_memory_clock = UINT64_C(0), .tcp_cache_size = 0, .num_sqc_per_wgp = 0, .sqc_data_cache_size = 0, .sqc_inst_cache_size = 0, .gl1c_cache_size = 0, .gl2c_cache_size = 0, - .mall_size = 0llu, + .mall_size = UINT64_C(0), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 67108864, - .usable_heap_size = 50491392, - .heap_usage = 51437568, - .max_allocation = 37868544, + .total_heap_size = UINT64_C(67108864), + .usable_heap_size = UINT64_C(50491392), + .heap_usage = UINT64_C(51437568), + .max_allocation = UINT64_C(37868544), }, .cpu_accessible_vram = { - .total_heap_size = 67108864, - .usable_heap_size = 50491392, - .heap_usage = 51437568, - .max_allocation = 37868544, + .total_heap_size = UINT64_C(67108864), + .usable_heap_size = UINT64_C(50491392), + .heap_usage = UINT64_C(51437568), + .max_allocation = UINT64_C(37868544), }, .gtt = { - .total_heap_size = 3057070080, - .usable_heap_size = 3052445696, - .heap_usage = 62390272, - .max_allocation = 2289334272, + .total_heap_size = UINT64_C(3057070080), + .usable_heap_size = UINT64_C(3052445696), + .heap_usage = UINT64_C(62390272), + .max_allocation = UINT64_C(2289334272), }, }, }, @@ -402,7 +402,7 @@ const struct amdgpu_device amdgpu_devices[] = { .num_hw_gfx_contexts = 8, .ids_flags = 0x1, .virtual_address_offset = 0x200000, - .virtual_address_max = 0xfffe00000llu, + .virtual_address_max = UINT64_C(0xfffe00000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -418,13 +418,13 @@ const struct amdgpu_device amdgpu_devices[] = { }, .mem = { .vram = { - .total_heap_size = 16ull << 20, + .total_heap_size = UINT64_C(16) << 20, }, .cpu_accessible_vram = { - .total_heap_size = 16ull << 20, + .total_heap_size = UINT64_C(16) << 20, }, .gtt = { - .total_heap_size = 3072ull << 20, + .total_heap_size = UINT64_C(3072) << 20, }, }, }, @@ -434,7 +434,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 10, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -443,7 +443,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 10, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0xf, @@ -474,8 +474,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 1, .num_shader_arrays_per_engine = 1, .gpu_counter_freq = 100000, - .max_engine_clock = 0llu, - .max_memory_clock = 0llu, + .max_engine_clock = UINT64_C(0), + .max_memory_clock = UINT64_C(0), .cu_active_number = 8, .cu_ao_mask = 0xff, .cu_bitmap = { @@ -488,9 +488,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 2, .num_hw_gfx_contexts = 8, .pcie_gen = 0, - .ids_flags = 0x1llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0x800000000000llu, + .ids_flags = UINT64_C(0x1), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0x800000000000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -499,10 +499,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 256, .vce_harvest_config = 0, .gc_double_offchip_lds_buf = 1, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -521,39 +521,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0x0, 0x0, 0x0, 0x0, }, { 0x0, 0x0, 0x0, 0x0, }, }, - .high_va_offset = 0xffff800000000000llu, - .high_va_max = 0xffffffffffe00000llu, + .high_va_offset = UINT64_C(0xffff800000000000), + .high_va_max = UINT64_C(0xffffffffffe00000), .pa_sc_tile_steering_override = 0, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 0llu, - .min_memory_clock = 0llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(0), + .min_memory_clock = UINT64_C(0), .tcp_cache_size = 0, .num_sqc_per_wgp = 0, .sqc_data_cache_size = 0, .sqc_inst_cache_size = 0, .gl1c_cache_size = 0, .gl2c_cache_size = 0, - .mall_size = 0llu, + .mall_size = UINT64_C(0), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 1073741824, - .usable_heap_size = 1040584704, - .heap_usage = 344141824, - .max_allocation = 780438528, + .total_heap_size = UINT64_C(1073741824), + .usable_heap_size = UINT64_C(1040584704), + .heap_usage = UINT64_C(344141824), + .max_allocation = UINT64_C(780438528), }, .cpu_accessible_vram = { - .total_heap_size = 1073741824, - .usable_heap_size = 1040584704, - .heap_usage = 344141824, - .max_allocation = 780438528, + .total_heap_size = UINT64_C(1073741824), + .usable_heap_size = UINT64_C(1040584704), + .heap_usage = UINT64_C(344141824), + .max_allocation = UINT64_C(780438528), }, .gtt = { - .total_heap_size = 8522825728, - .usable_heap_size = 8511004672, - .heap_usage = 79179776, - .max_allocation = 6383253504, + .total_heap_size = UINT64_C(8522825728), + .usable_heap_size = UINT64_C(8511004672), + .heap_usage = UINT64_C(79179776), + .max_allocation = UINT64_C(6383253504), }, }, }, @@ -563,7 +563,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 10, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -572,7 +572,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 10, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0xf, @@ -603,8 +603,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 1, .num_shader_arrays_per_engine = 1, .gpu_counter_freq = 100000, - .max_engine_clock = 200000llu, - .max_memory_clock = 2400000llu, + .max_engine_clock = UINT64_C(200000), + .max_memory_clock = UINT64_C(2400000), .cu_active_number = 2, .cu_ao_mask = 0x3, .cu_bitmap = { @@ -617,9 +617,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 1, .num_hw_gfx_contexts = 8, .pcie_gen = 4, - .ids_flags = 0x1llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0x800000000000llu, + .ids_flags = UINT64_C(0x1), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0x800000000000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -628,10 +628,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 128, .vce_harvest_config = 0, .gc_double_offchip_lds_buf = 1, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -650,39 +650,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0x0, 0x0, 0x0, 0x0, }, { 0x0, 0x0, 0x0, 0x0, }, }, - .high_va_offset = 0xffff800000000000llu, - .high_va_max = 0xffffffffffe00000llu, + .high_va_offset = UINT64_C(0xffff800000000000), + .high_va_max = UINT64_C(0xffffffffffe00000), .pa_sc_tile_steering_override = 0, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 200000llu, - .min_memory_clock = 2400000llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(200000), + .min_memory_clock = UINT64_C(2400000), .tcp_cache_size = 0, .num_sqc_per_wgp = 0, .sqc_data_cache_size = 0, .sqc_inst_cache_size = 0, .gl1c_cache_size = 0, .gl2c_cache_size = 0, - .mall_size = 0llu, + .mall_size = UINT64_C(0), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 536870912, - .usable_heap_size = 512081920, - .heap_usage = 30093312, - .max_allocation = 384061440, + .total_heap_size = UINT64_C(536870912), + .usable_heap_size = UINT64_C(512081920), + .heap_usage = UINT64_C(30093312), + .max_allocation = UINT64_C(384061440), }, .cpu_accessible_vram = { - .total_heap_size = 536870912, - .usable_heap_size = 512081920, - .heap_usage = 30093312, - .max_allocation = 384061440, + .total_heap_size = UINT64_C(536870912), + .usable_heap_size = UINT64_C(512081920), + .heap_usage = UINT64_C(30093312), + .max_allocation = UINT64_C(384061440), }, .gtt = { - .total_heap_size = 33254252544, - .usable_heap_size = 33241997312, - .heap_usage = 14360576, - .max_allocation = 24931497984, + .total_heap_size = UINT64_C(33254252544), + .usable_heap_size = UINT64_C(33241997312), + .heap_usage = UINT64_C(14360576), + .max_allocation = UINT64_C(24931497984), }, }, }, @@ -692,7 +692,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 8, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -701,7 +701,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 8, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0xf, @@ -793,8 +793,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 4, .num_shader_arrays_per_engine = 1, .gpu_counter_freq = 25000, - .max_engine_clock = 1360000llu, - .max_memory_clock = 2000000llu, + .max_engine_clock = UINT64_C(1360000), + .max_memory_clock = UINT64_C(2000000), .cu_active_number = 36, .cu_ao_mask = 0x1ff01ff, .cu_bitmap = { @@ -807,9 +807,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 8, .num_hw_gfx_contexts = 8, .pcie_gen = 0, - .ids_flags = 0x0llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0x1fffe00000llu, + .ids_flags = UINT64_C(0x0), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0x1fffe00000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -818,10 +818,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 256, .vce_harvest_config = 2, .gc_double_offchip_lds_buf = 1, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -840,39 +840,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0x1ff, 0x0, 0x0, 0x0, }, { 0x1ff, 0x0, 0x0, 0x0, }, }, - .high_va_offset = 0x0llu, - .high_va_max = 0x0llu, + .high_va_offset = UINT64_C(0x0), + .high_va_max = UINT64_C(0x0), .pa_sc_tile_steering_override = 0, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 0llu, - .min_memory_clock = 0llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(0), + .min_memory_clock = UINT64_C(0), .tcp_cache_size = 0, .num_sqc_per_wgp = 0, .sqc_data_cache_size = 0, .sqc_inst_cache_size = 0, .gl1c_cache_size = 0, .gl2c_cache_size = 0, - .mall_size = 0llu, + .mall_size = UINT64_C(0), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 8589934592, - .usable_heap_size = 8576106496, - .heap_usage = 267620352, - .max_allocation = 6432079872, + .total_heap_size = UINT64_C(8589934592), + .usable_heap_size = UINT64_C(8576106496), + .heap_usage = UINT64_C(267620352), + .max_allocation = UINT64_C(6432079872), }, .cpu_accessible_vram = { - .total_heap_size = 268435456, - .usable_heap_size = 262995968, - .heap_usage = 17641472, - .max_allocation = 197246976, + .total_heap_size = UINT64_C(268435456), + .usable_heap_size = UINT64_C(262995968), + .heap_usage = UINT64_C(17641472), + .max_allocation = UINT64_C(197246976), }, .gtt = { - .total_heap_size = 16776243200, - .usable_heap_size = 16766920704, - .heap_usage = 80318464, - .max_allocation = 12575190528, + .total_heap_size = UINT64_C(16776243200), + .usable_heap_size = UINT64_C(16766920704), + .heap_usage = UINT64_C(80318464), + .max_allocation = UINT64_C(12575190528), }, }, }, @@ -882,7 +882,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 8, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -891,7 +891,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 8, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0xf, @@ -977,8 +977,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 2, .num_shader_arrays_per_engine = 1, .gpu_counter_freq = 25000, - .max_engine_clock = 1183000llu, - .max_memory_clock = 1750000llu, + .max_engine_clock = UINT64_C(1183000), + .max_memory_clock = UINT64_C(1750000), .cu_active_number = 8, .cu_ao_mask = 0x1e001e, .cu_bitmap = { @@ -991,9 +991,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 4, .num_hw_gfx_contexts = 8, .pcie_gen = 3, - .ids_flags = 0x0llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0x3fffe00000llu, + .ids_flags = UINT64_C(0x0), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0x3fffe00000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -1002,10 +1002,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 128, .vce_harvest_config = 2, .gc_double_offchip_lds_buf = 1, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -1024,39 +1024,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0x0, 0x0, 0x0, 0x0, }, { 0x0, 0x0, 0x0, 0x0, }, }, - .high_va_offset = 0x0llu, - .high_va_max = 0x0llu, + .high_va_offset = UINT64_C(0x0), + .high_va_max = UINT64_C(0x0), .pa_sc_tile_steering_override = 0, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 214000llu, - .min_memory_clock = 300000llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(214000), + .min_memory_clock = UINT64_C(300000), .tcp_cache_size = 0, .num_sqc_per_wgp = 0, .sqc_data_cache_size = 0, .sqc_inst_cache_size = 0, .gl1c_cache_size = 0, .gl2c_cache_size = 0, - .mall_size = 0llu, + .mall_size = UINT64_C(0), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 4294967296, - .usable_heap_size = 4281139200, - .heap_usage = 5963776, - .max_allocation = 3210854400, + .total_heap_size = UINT64_C(4294967296), + .usable_heap_size = UINT64_C(4281139200), + .heap_usage = UINT64_C(5963776), + .max_allocation = UINT64_C(3210854400), }, .cpu_accessible_vram = { - .total_heap_size = 4294967296, - .usable_heap_size = 4281139200, - .heap_usage = 5963776, - .max_allocation = 3210854400, + .total_heap_size = UINT64_C(4294967296), + .usable_heap_size = UINT64_C(4281139200), + .heap_usage = UINT64_C(5963776), + .max_allocation = UINT64_C(3210854400), }, .gtt = { - .total_heap_size = 33254252544, - .usable_heap_size = 33249120256, - .heap_usage = 17903616, - .max_allocation = 24936840192, + .total_heap_size = UINT64_C(33254252544), + .usable_heap_size = UINT64_C(33249120256), + .heap_usage = UINT64_C(17903616), + .max_allocation = UINT64_C(24936840192), }, }, }, @@ -1066,7 +1066,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 9, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -1075,7 +1075,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 9, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0xf, @@ -1106,8 +1106,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 4, .num_shader_arrays_per_engine = 1, .gpu_counter_freq = 27000, - .max_engine_clock = 1630000llu, - .max_memory_clock = 945000llu, + .max_engine_clock = UINT64_C(1630000), + .max_memory_clock = UINT64_C(945000), .cu_active_number = 64, .cu_ao_mask = 0xffffffff, .cu_bitmap = { @@ -1120,9 +1120,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 16, .num_hw_gfx_contexts = 8, .pcie_gen = 0, - .ids_flags = 0x0llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0x800000000000llu, + .ids_flags = UINT64_C(0x0), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0x800000000000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -1131,10 +1131,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 2048, .vce_harvest_config = 0, .gc_double_offchip_lds_buf = 1, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -1153,39 +1153,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0xffff, 0x0, 0x0, 0x0, }, { 0xffff, 0x0, 0x0, 0x0, }, }, - .high_va_offset = 0xffff800000000000llu, - .high_va_max = 0xffffffffffe00000llu, + .high_va_offset = UINT64_C(0xffff800000000000), + .high_va_max = UINT64_C(0xffffffffffe00000), .pa_sc_tile_steering_override = 0, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 0llu, - .min_memory_clock = 0llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(0), + .min_memory_clock = UINT64_C(0), .tcp_cache_size = 0, .num_sqc_per_wgp = 0, .sqc_data_cache_size = 0, .sqc_inst_cache_size = 0, .gl1c_cache_size = 0, .gl2c_cache_size = 0, - .mall_size = 0llu, + .mall_size = UINT64_C(0), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 8573157376, - .usable_heap_size = 8556453888, - .heap_usage = 39575552, - .max_allocation = 6417340416, + .total_heap_size = UINT64_C(8573157376), + .usable_heap_size = UINT64_C(8556453888), + .heap_usage = UINT64_C(39575552), + .max_allocation = UINT64_C(6417340416), }, .cpu_accessible_vram = { - .total_heap_size = 268435456, - .usable_heap_size = 260120576, - .heap_usage = 30138368, - .max_allocation = 195090432, + .total_heap_size = UINT64_C(268435456), + .usable_heap_size = UINT64_C(260120576), + .heap_usage = UINT64_C(30138368), + .max_allocation = UINT64_C(195090432), }, .gtt = { - .total_heap_size = 8359135232, - .usable_heap_size = 8346802176, - .heap_usage = 22892544, - .max_allocation = 6260101632, + .total_heap_size = UINT64_C(8359135232), + .usable_heap_size = UINT64_C(8346802176), + .heap_usage = UINT64_C(22892544), + .max_allocation = UINT64_C(6260101632), }, }, }, @@ -1195,7 +1195,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 10, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -1204,7 +1204,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 10, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0xf, @@ -1235,8 +1235,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 2, .num_shader_arrays_per_engine = 2, .gpu_counter_freq = 100000, - .max_engine_clock = 2100000llu, - .max_memory_clock = 875000llu, + .max_engine_clock = UINT64_C(2100000), + .max_memory_clock = UINT64_C(875000), .cu_active_number = 40, .cu_ao_mask = 0xffffffff, .cu_bitmap = { @@ -1249,9 +1249,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 16, .num_hw_gfx_contexts = 8, .pcie_gen = 0, - .ids_flags = 0x0llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0x800000000000llu, + .ids_flags = UINT64_C(0x0), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0x800000000000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -1260,10 +1260,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 256, .vce_harvest_config = 0, .gc_double_offchip_lds_buf = 1, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -1282,39 +1282,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0x0, 0x0, 0x0, 0x0, }, { 0x0, 0x0, 0x0, 0x0, }, }, - .high_va_offset = 0xffff800000000000llu, - .high_va_max = 0xffffffffffe00000llu, + .high_va_offset = UINT64_C(0xffff800000000000), + .high_va_max = UINT64_C(0xffffffffffe00000), .pa_sc_tile_steering_override = 1187840, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 0llu, - .min_memory_clock = 0llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(0), + .min_memory_clock = UINT64_C(0), .tcp_cache_size = 0, .num_sqc_per_wgp = 0, .sqc_data_cache_size = 0, .sqc_inst_cache_size = 0, .gl1c_cache_size = 0, .gl2c_cache_size = 0, - .mall_size = 0llu, + .mall_size = UINT64_C(0), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 8573157376, - .usable_heap_size = 8553127936, - .heap_usage = 11644928, - .max_allocation = 6414845952, + .total_heap_size = UINT64_C(8573157376), + .usable_heap_size = UINT64_C(8553127936), + .heap_usage = UINT64_C(11644928), + .max_allocation = UINT64_C(6414845952), }, .cpu_accessible_vram = { - .total_heap_size = 268435456, - .usable_heap_size = 256860160, - .heap_usage = 11579392, - .max_allocation = 192645120, + .total_heap_size = UINT64_C(268435456), + .usable_heap_size = UINT64_C(256860160), + .heap_usage = UINT64_C(11579392), + .max_allocation = UINT64_C(192645120), }, .gtt = { - .total_heap_size = 8359135232, - .usable_heap_size = 8347318272, - .heap_usage = 22102016, - .max_allocation = 6260488704, + .total_heap_size = UINT64_C(8359135232), + .usable_heap_size = UINT64_C(8347318272), + .heap_usage = UINT64_C(22102016), + .max_allocation = UINT64_C(6260488704), }, }, }, @@ -1324,7 +1324,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 11, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -1333,7 +1333,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 11, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0xf, @@ -1364,8 +1364,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 6, .num_shader_arrays_per_engine = 2, .gpu_counter_freq = 100000, - .max_engine_clock = 2371000llu, - .max_memory_clock = 1249000llu, + .max_engine_clock = UINT64_C(2371000), + .max_memory_clock = UINT64_C(1249000), .cu_active_number = 96, .cu_ao_mask = 0x0, .cu_bitmap = { @@ -1378,9 +1378,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 24, .num_hw_gfx_contexts = 8, .pcie_gen = 4, - .ids_flags = 0x0llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0x800000000000llu, + .ids_flags = UINT64_C(0x0), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0x800000000000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -1389,10 +1389,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 384, .vce_harvest_config = 0, .gc_double_offchip_lds_buf = 0, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -1411,39 +1411,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0x0, 0x0, 0x0, 0x0, }, { 0x0, 0x0, 0x0, 0x0, }, }, - .high_va_offset = 0xffff800000000000llu, - .high_va_max = 0xffffffffffe00000llu, + .high_va_offset = UINT64_C(0xffff800000000000), + .high_va_max = UINT64_C(0xffffffffffe00000), .pa_sc_tile_steering_override = 0, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 500000llu, - .min_memory_clock = 96000llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(500000), + .min_memory_clock = UINT64_C(96000), .tcp_cache_size = 32, .num_sqc_per_wgp = 1, .sqc_data_cache_size = 16, .sqc_inst_cache_size = 32, .gl1c_cache_size = 256, .gl2c_cache_size = 6144, - .mall_size = 100663296llu, + .mall_size = UINT64_C(100663296), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 25753026560, - .usable_heap_size = 25681096704, - .heap_usage = 7515435008, - .max_allocation = 19260822528, + .total_heap_size = UINT64_C(25753026560), + .usable_heap_size = UINT64_C(25681096704), + .heap_usage = UINT64_C(7515435008), + .max_allocation = UINT64_C(19260822528), }, .cpu_accessible_vram = { - .total_heap_size = 25753026560, - .usable_heap_size = 25681096704, - .heap_usage = 7515435008, - .max_allocation = 19260822528, + .total_heap_size = UINT64_C(25753026560), + .usable_heap_size = UINT64_C(25681096704), + .heap_usage = UINT64_C(7515435008), + .max_allocation = UINT64_C(19260822528), }, .gtt = { - .total_heap_size = 33254252544, - .usable_heap_size = 33240895488, - .heap_usage = 142462976, - .max_allocation = 24930671616, + .total_heap_size = UINT64_C(33254252544), + .usable_heap_size = UINT64_C(33240895488), + .heap_usage = UINT64_C(142462976), + .max_allocation = UINT64_C(24930671616), }, }, }, @@ -1453,7 +1453,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 10, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -1462,7 +1462,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 10, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0xf, @@ -1493,8 +1493,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 4, .num_shader_arrays_per_engine = 2, .gpu_counter_freq = 100000, - .max_engine_clock = 2475000llu, - .max_memory_clock = 1000000llu, + .max_engine_clock = UINT64_C(2475000), + .max_memory_clock = UINT64_C(1000000), .cu_active_number = 60, .cu_ao_mask = 0x3ffff, .cu_bitmap = { @@ -1507,9 +1507,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 16, .num_hw_gfx_contexts = 8, .pcie_gen = 3, - .ids_flags = 0x0llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0x800000000000llu, + .ids_flags = UINT64_C(0x0), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0x800000000000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -1518,10 +1518,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 256, .vce_harvest_config = 0, .gc_double_offchip_lds_buf = 1, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -1540,39 +1540,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0x3ff, 0x3ff, 0x0, 0x0, }, { 0x3ff, 0x3ff, 0x0, 0x0, }, }, - .high_va_offset = 0xffff800000000000llu, - .high_va_max = 0xffffffffffe00000llu, + .high_va_offset = UINT64_C(0xffff800000000000), + .high_va_max = UINT64_C(0xffffffffffe00000), .pa_sc_tile_steering_override = 0, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 500000llu, - .min_memory_clock = 96000llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(500000), + .min_memory_clock = UINT64_C(96000), .tcp_cache_size = 0, .num_sqc_per_wgp = 0, .sqc_data_cache_size = 0, .sqc_inst_cache_size = 0, .gl1c_cache_size = 0, .gl2c_cache_size = 0, - .mall_size = 134217728llu, + .mall_size = UINT64_C(134217728), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 17163091968, - .usable_heap_size = 17128448000, - .heap_usage = 817770496, - .max_allocation = 12846336000, + .total_heap_size = UINT64_C(17163091968), + .usable_heap_size = UINT64_C(17128448000), + .heap_usage = UINT64_C(817770496), + .max_allocation = UINT64_C(12846336000), }, .cpu_accessible_vram = { - .total_heap_size = 268435456, - .usable_heap_size = 273055744, - .heap_usage = 246521856, - .max_allocation = 204791808, + .total_heap_size = UINT64_C(268435456), + .usable_heap_size = UINT64_C(273055744), + .heap_usage = UINT64_C(246521856), + .max_allocation = UINT64_C(204791808), }, .gtt = { - .total_heap_size = 16746784768, - .usable_heap_size = 16733624320, - .heap_usage = 499445760, - .max_allocation = 12550218240, + .total_heap_size = UINT64_C(16746784768), + .usable_heap_size = UINT64_C(16733624320), + .heap_usage = UINT64_C(499445760), + .max_allocation = UINT64_C(12550218240), }, }, }, @@ -1582,7 +1582,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 6, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -1591,7 +1591,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 6, .hw_ip_version_minor = 0, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x3, @@ -1659,8 +1659,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 2, .num_shader_arrays_per_engine = 2, .gpu_counter_freq = 27000, - .max_engine_clock = 1100000llu, - .max_memory_clock = 1250000llu, + .max_engine_clock = UINT64_C(1100000), + .max_memory_clock = UINT64_C(1250000), .cu_active_number = 20, .cu_ao_mask = 0x1f1f1f1f, .cu_bitmap = { @@ -1673,9 +1673,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 8, .num_hw_gfx_contexts = 8, .pcie_gen = 3, - .ids_flags = 0x0llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0xfffe00000llu, + .ids_flags = UINT64_C(0x0), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0xfffe00000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -1684,10 +1684,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 256, .vce_harvest_config = 0, .gc_double_offchip_lds_buf = 0, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -1706,39 +1706,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0x0, 0x0, 0x0, 0x0, }, { 0x0, 0x0, 0x0, 0x0, }, }, - .high_va_offset = 0x0llu, - .high_va_max = 0x0llu, + .high_va_offset = UINT64_C(0x0), + .high_va_max = UINT64_C(0x0), .pa_sc_tile_steering_override = 0, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 300000llu, - .min_memory_clock = 150000llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(300000), + .min_memory_clock = UINT64_C(150000), .tcp_cache_size = 0, .num_sqc_per_wgp = 0, .sqc_data_cache_size = 0, .sqc_inst_cache_size = 0, .gl1c_cache_size = 0, .gl2c_cache_size = 0, - .mall_size = 0llu, + .mall_size = UINT64_C(0), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 2147483648, - .usable_heap_size = 2134118400, - .heap_usage = 5238784, - .max_allocation = 1600588800, + .total_heap_size = UINT64_C(2147483648), + .usable_heap_size = UINT64_C(2134118400), + .heap_usage = UINT64_C(5238784), + .max_allocation = UINT64_C(1600588800), }, .cpu_accessible_vram = { - .total_heap_size = 268435456, - .usable_heap_size = 263458816, - .heap_usage = 4976640, - .max_allocation = 197594112, + .total_heap_size = UINT64_C(268435456), + .usable_heap_size = UINT64_C(263458816), + .heap_usage = UINT64_C(4976640), + .max_allocation = UINT64_C(197594112), }, .gtt = { - .total_heap_size = 8363028480, - .usable_heap_size = 8359759872, - .heap_usage = 3530752, - .max_allocation = 6269819904, + .total_heap_size = UINT64_C(8363028480), + .usable_heap_size = UINT64_C(8359759872), + .heap_usage = UINT64_C(3530752), + .max_allocation = UINT64_C(6269819904), }, }, }, @@ -1748,7 +1748,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_gfx = { .hw_ip_version_major = 7, .hw_ip_version_minor = 2, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0x1, @@ -1757,7 +1757,7 @@ const struct amdgpu_device amdgpu_devices[] = { .hw_ip_compute = { .hw_ip_version_major = 7, .hw_ip_version_minor = 2, - .capabilities_flags = 0llu, + .capabilities_flags = UINT64_C(0), .ib_start_alignment = 32, .ib_size_alignment = 32, .available_rings = 0xf, @@ -1843,8 +1843,8 @@ const struct amdgpu_device amdgpu_devices[] = { .num_shader_engines = 2, .num_shader_arrays_per_engine = 1, .gpu_counter_freq = 27000, - .max_engine_clock = 1075000llu, - .max_memory_clock = 1600000llu, + .max_engine_clock = UINT64_C(1075000), + .max_memory_clock = UINT64_C(1600000), .cu_active_number = 14, .cu_ao_mask = 0x7f007f, .cu_bitmap = { @@ -1857,9 +1857,9 @@ const struct amdgpu_device amdgpu_devices[] = { .num_rb_pipes = 4, .num_hw_gfx_contexts = 8, .pcie_gen = 3, - .ids_flags = 0x0llu, - .virtual_address_offset = 0x200000llu, - .virtual_address_max = 0x1fffe00000llu, + .ids_flags = UINT64_C(0x0), + .virtual_address_offset = UINT64_C(0x200000), + .virtual_address_max = UINT64_C(0x1fffe00000), .virtual_address_alignment = 4096, .pte_fragment_size = 2097152, .gart_page_size = 4096, @@ -1868,10 +1868,10 @@ const struct amdgpu_device amdgpu_devices[] = { .vram_bit_width = 128, .vce_harvest_config = 0, .gc_double_offchip_lds_buf = 1, - .prim_buf_gpu_addr = 0llu, - .pos_buf_gpu_addr = 0llu, - .cntl_sb_buf_gpu_addr = 0llu, - .param_buf_gpu_addr = 0llu, + .prim_buf_gpu_addr = UINT64_C(0), + .pos_buf_gpu_addr = UINT64_C(0), + .cntl_sb_buf_gpu_addr = UINT64_C(0), + .param_buf_gpu_addr = UINT64_C(0), .prim_buf_size = 0, .pos_buf_size = 0, .cntl_sb_buf_size = 0, @@ -1890,39 +1890,39 @@ const struct amdgpu_device amdgpu_devices[] = { { 0x0, 0x0, 0x0, 0x0, }, { 0x0, 0x0, 0x0, 0x0, }, }, - .high_va_offset = 0x0llu, - .high_va_max = 0x0llu, + .high_va_offset = UINT64_C(0x0), + .high_va_max = UINT64_C(0x0), .pa_sc_tile_steering_override = 0, - .tcc_disabled_mask = 0llu, - .min_engine_clock = 300000llu, - .min_memory_clock = 150000llu, + .tcc_disabled_mask = UINT64_C(0), + .min_engine_clock = UINT64_C(300000), + .min_memory_clock = UINT64_C(150000), .tcp_cache_size = 0, .num_sqc_per_wgp = 0, .sqc_data_cache_size = 0, .sqc_inst_cache_size = 0, .gl1c_cache_size = 0, .gl2c_cache_size = 0, - .mall_size = 0llu, + .mall_size = UINT64_C(0), .enabled_rb_pipes_mask_hi = 0, }, .mem = { .vram = { - .total_heap_size = 2147483648, - .usable_heap_size = 2118266880, - .heap_usage = 21352448, - .max_allocation = 1588700160, + .total_heap_size = UINT64_C(2147483648), + .usable_heap_size = UINT64_C(2118266880), + .heap_usage = UINT64_C(21352448), + .max_allocation = UINT64_C(1588700160), }, .cpu_accessible_vram = { - .total_heap_size = 268435456, - .usable_heap_size = 255901696, - .heap_usage = 20828160, - .max_allocation = 191926272, + .total_heap_size = UINT64_C(268435456), + .usable_heap_size = UINT64_C(255901696), + .heap_usage = UINT64_C(20828160), + .max_allocation = UINT64_C(191926272), }, .gtt = { - .total_heap_size = 16746776576, - .usable_heap_size = 16743417856, - .heap_usage = 3883008, - .max_allocation = 12557563392, + .total_heap_size = UINT64_C(16746776576), + .usable_heap_size = UINT64_C(16743417856), + .heap_usage = UINT64_C(3883008), + .max_allocation = UINT64_C(12557563392), }, }, } diff --git a/src/amd/drm-shim/amdgpu_dump_states.c b/src/amd/drm-shim/amdgpu_dump_states.c index 0d999d5eb6a..cd393464648 100644 --- a/src/amd/drm-shim/amdgpu_dump_states.c +++ b/src/amd/drm-shim/amdgpu_dump_states.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "drm-uapi/amdgpu_drm.h" #include "util/macros.h" @@ -102,22 +103,26 @@ amdgpu_dump_memory(int fd) printf(".mem = {\n"); printf(" .vram = {\n"); - printf(" .total_heap_size = %llu,\n", info.vram.total_heap_size); - printf(" .usable_heap_size = %llu,\n", info.vram.usable_heap_size); - printf(" .heap_usage = %llu,\n", info.vram.heap_usage); - printf(" .max_allocation = %llu,\n", info.vram.max_allocation); + printf(" .total_heap_size = UINT64_C(%"PRIu64"),\n", (uint64_t)info.vram.total_heap_size); + printf(" .usable_heap_size = UINT64_C(%"PRIu64"),\n", (uint64_t)info.vram.usable_heap_size); + printf(" .heap_usage = UINT64_C(%"PRIu64"),\n", (uint64_t)info.vram.heap_usage); + printf(" .max_allocation = UINT64_C(%"PRIu64"),\n", (uint64_t)info.vram.max_allocation); printf(" },\n"); printf(" .cpu_accessible_vram = {\n"); - printf(" .total_heap_size = %llu,\n", info.cpu_accessible_vram.total_heap_size); - printf(" .usable_heap_size = %llu,\n", info.cpu_accessible_vram.usable_heap_size); - printf(" .heap_usage = %llu,\n", info.cpu_accessible_vram.heap_usage); - printf(" .max_allocation = %llu,\n", info.cpu_accessible_vram.max_allocation); + printf(" .total_heap_size = UINT64_C(%"PRIu64"),\n", + (uint64_t)info.cpu_accessible_vram.total_heap_size); + printf(" .usable_heap_size = UINT64_C(%"PRIu64"),\n", + (uint64_t)info.cpu_accessible_vram.usable_heap_size); + printf(" .heap_usage = UINT64_C(%"PRIu64"),\n", + (uint64_t)info.cpu_accessible_vram.heap_usage); + printf(" .max_allocation = UINT64_C(%"PRIu64"),\n", + (uint64_t)info.cpu_accessible_vram.max_allocation); printf(" },\n"); printf(" .gtt = {\n"); - printf(" .total_heap_size = %llu,\n", info.gtt.total_heap_size); - printf(" .usable_heap_size = %llu,\n", info.gtt.usable_heap_size); - printf(" .heap_usage = %llu,\n", info.gtt.heap_usage); - printf(" .max_allocation = %llu,\n", info.gtt.max_allocation); + printf(" .total_heap_size = UINT64_C(%"PRIu64"),\n", (uint64_t)info.gtt.total_heap_size); + printf(" .usable_heap_size = UINT64_C(%"PRIu64"),\n", (uint64_t)info.gtt.usable_heap_size); + printf(" .heap_usage = UINT64_C(%"PRIu64"),\n", (uint64_t)info.gtt.heap_usage); + printf(" .max_allocation = UINT64_C(%"PRIu64"),\n", (uint64_t)info.gtt.max_allocation); printf(" },\n"); printf("},\n"); } @@ -174,8 +179,8 @@ amdgpu_dump_dev_info(int fd) printf(" .num_shader_engines = %u,\n", info.num_shader_engines); printf(" .num_shader_arrays_per_engine = %u,\n", info.num_shader_arrays_per_engine); printf(" .gpu_counter_freq = %u,\n", info.gpu_counter_freq); - printf(" .max_engine_clock = %llullu,\n", info.max_engine_clock); - printf(" .max_memory_clock = %llullu,\n", info.max_memory_clock); + printf(" .max_engine_clock = UINT64_C(%"PRIu64"),\n", (uint64_t)info.max_engine_clock); + printf(" .max_memory_clock = UINT64_C(%"PRIu64"),\n", (uint64_t)info.max_memory_clock); printf(" .cu_active_number = %u,\n", info.cu_active_number); printf(" .cu_ao_mask = 0x%x,\n", info.cu_ao_mask); @@ -192,9 +197,10 @@ amdgpu_dump_dev_info(int fd) printf(" .num_rb_pipes = %u,\n", info.num_rb_pipes); printf(" .num_hw_gfx_contexts = %u,\n", info.num_hw_gfx_contexts); printf(" .pcie_gen = %u,\n", info.pcie_gen); - printf(" .ids_flags = 0x%llxllu,\n", info.ids_flags); - printf(" .virtual_address_offset = 0x%llxllu,\n", info.virtual_address_offset); - printf(" .virtual_address_max = 0x%llxllu,\n", info.virtual_address_max); + printf(" .ids_flags = UINT64_C(0x%"PRIx64"),\n", (uint64_t)info.ids_flags); + printf(" .virtual_address_offset = UINT64_C(0x%"PRIx64"),\n", + (uint64_t)info.virtual_address_offset); + printf(" .virtual_address_max = UINT64_C(0x%"PRIx64"),\n", (uint64_t)info.virtual_address_max); printf(" .virtual_address_alignment = %u,\n", info.virtual_address_alignment); printf(" .pte_fragment_size = %u,\n", info.pte_fragment_size); printf(" .gart_page_size = %u,\n", info.gart_page_size); @@ -203,10 +209,10 @@ amdgpu_dump_dev_info(int fd) printf(" .vram_bit_width = %u,\n", info.vram_bit_width); printf(" .vce_harvest_config = %u,\n", info.vce_harvest_config); printf(" .gc_double_offchip_lds_buf = %u,\n", info.gc_double_offchip_lds_buf); - printf(" .prim_buf_gpu_addr = %llullu,\n", info.prim_buf_gpu_addr); - printf(" .pos_buf_gpu_addr = %llullu,\n", info.pos_buf_gpu_addr); - printf(" .cntl_sb_buf_gpu_addr = %llullu,\n", info.cntl_sb_buf_gpu_addr); - printf(" .param_buf_gpu_addr = %llullu,\n", info.param_buf_gpu_addr); + printf(" .prim_buf_gpu_addr = UINT64_C(%"PRIu64"),\n", (uint64_t)info.prim_buf_gpu_addr); + printf(" .pos_buf_gpu_addr = UINT64_C(%"PRIu64"),\n", (uint64_t)info.pos_buf_gpu_addr); + printf(" .cntl_sb_buf_gpu_addr = UINT64_C(%"PRIu64"),\n", (uint64_t)info.cntl_sb_buf_gpu_addr); + printf(" .param_buf_gpu_addr = UINT64_C(%"PRIu64"),\n", (uint64_t)info.param_buf_gpu_addr); printf(" .prim_buf_size = %u,\n", info.prim_buf_size); printf(" .pos_buf_size = %u,\n", info.pos_buf_size); printf(" .cntl_sb_buf_size = %u,\n", info.cntl_sb_buf_size); @@ -229,19 +235,19 @@ amdgpu_dump_dev_info(int fd) } printf(" },\n"); - printf(" .high_va_offset = 0x%llxllu,\n", info.high_va_offset); - printf(" .high_va_max = 0x%llxllu,\n", info.high_va_max); + printf(" .high_va_offset = UINT64_C(0x%"PRIx64"),\n", (uint64_t)info.high_va_offset); + printf(" .high_va_max = UINT64_C(0x%"PRIx64"),\n", (uint64_t)info.high_va_max); printf(" .pa_sc_tile_steering_override = %u,\n", info.pa_sc_tile_steering_override); - printf(" .tcc_disabled_mask = %llullu,\n", info.tcc_disabled_mask); - printf(" .min_engine_clock = %llullu,\n", info.min_engine_clock); - printf(" .min_memory_clock = %llullu,\n", info.min_memory_clock); + printf(" .tcc_disabled_mask = UINT64_C(%"PRIu64"),\n", (uint64_t)info.tcc_disabled_mask); + printf(" .min_engine_clock = UINT64_C(%"PRIu64"),\n", (uint64_t)info.min_engine_clock); + printf(" .min_memory_clock = UINT64_C(%"PRIu64"),\n", (uint64_t)info.min_memory_clock); printf(" .tcp_cache_size = %u,\n", info.tcp_cache_size); printf(" .num_sqc_per_wgp = %u,\n", info.num_sqc_per_wgp); printf(" .sqc_data_cache_size = %u,\n", info.sqc_data_cache_size); printf(" .sqc_inst_cache_size = %u,\n", info.sqc_inst_cache_size); printf(" .gl1c_cache_size = %u,\n", info.gl1c_cache_size); printf(" .gl2c_cache_size = %u,\n", info.gl2c_cache_size); - printf(" .mall_size = %llullu,\n", info.mall_size); + printf(" .mall_size = UINT64_C(%"PRIu64"),\n", (uint64_t)info.mall_size); printf(" .enabled_rb_pipes_mask_hi = %u,\n", info.enabled_rb_pipes_mask_hi); printf("},\n"); } @@ -366,7 +372,7 @@ amdgpu_dump_hw_ips(int fd) printf(".hw_ip_%s = {\n", hw_ips[i].name); printf(" .hw_ip_version_major = %u,\n", info.hw_ip_version_major); printf(" .hw_ip_version_minor = %u,\n", info.hw_ip_version_minor); - printf(" .capabilities_flags = %llullu,\n", info.capabilities_flags); + printf(" .capabilities_flags = UINT64_C(%"PRIu64"),\n", (uint64_t)info.capabilities_flags); printf(" .ib_start_alignment = %u,\n", info.ib_start_alignment); printf(" .ib_size_alignment = %u,\n", info.ib_size_alignment); printf(" .available_rings = 0x%x,\n", info.available_rings);