ac/nir: add ac_nir_lower_legacy_gs
For legacy (non-NGG) GS to lower outputs to memory stores and add shader query when required. Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20158>
This commit is contained in:
Qiang Yu
@@ -438,3 +438,231 @@ ac_nir_gs_shader_query(nir_builder *b,
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nir_pop_if(b, if_shader_query);
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return true;
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}
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typedef struct {
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nir_ssa_def *outputs[64][4];
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nir_ssa_def *outputs_16bit_lo[16][4];
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nir_ssa_def *outputs_16bit_hi[16][4];
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ac_nir_gs_output_info *info;
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nir_ssa_def *vertex_count[4];
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nir_ssa_def *primitive_count[4];
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} lower_legacy_gs_state;
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static bool
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lower_legacy_gs_store_output(nir_builder *b, nir_intrinsic_instr *intrin,
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lower_legacy_gs_state *s)
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{
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/* Assume:
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* - the shader used nir_lower_io_to_temporaries
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* - 64-bit outputs are lowered
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* - no indirect indexing is present
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*/
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assert(nir_src_is_const(intrin->src[1]) && !nir_src_as_uint(intrin->src[1]));
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b->cursor = nir_before_instr(&intrin->instr);
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unsigned component = nir_intrinsic_component(intrin);
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unsigned write_mask = nir_intrinsic_write_mask(intrin);
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nir_io_semantics sem = nir_intrinsic_io_semantics(intrin);
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nir_ssa_def **outputs;
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if (sem.location < VARYING_SLOT_VAR0_16BIT) {
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outputs = s->outputs[sem.location];
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} else {
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unsigned index = sem.location - VARYING_SLOT_VAR0_16BIT;
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if (sem.high_16bits)
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outputs = s->outputs_16bit_hi[index];
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else
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outputs = s->outputs_16bit_lo[index];
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}
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nir_ssa_def *store_val = intrin->src[0].ssa;
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/* 64bit output has been lowered to 32bit */
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assert(store_val->bit_size <= 32);
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u_foreach_bit (i, write_mask) {
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unsigned comp = component + i;
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outputs[comp] = nir_channel(b, store_val, i);
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}
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nir_instr_remove(&intrin->instr);
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return true;
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}
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static bool
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lower_legacy_gs_emit_vertex_with_counter(nir_builder *b, nir_intrinsic_instr *intrin,
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lower_legacy_gs_state *s)
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{
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b->cursor = nir_before_instr(&intrin->instr);
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unsigned stream = nir_intrinsic_stream_id(intrin);
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nir_ssa_def *vtxidx = intrin->src[0].ssa;
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nir_ssa_def *gsvs_ring = nir_load_ring_gsvs_amd(b, .stream_id = stream);
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nir_ssa_def *soffset = nir_load_ring_gs2vs_offset_amd(b);
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unsigned offset = 0;
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u_foreach_bit64 (i, b->shader->info.outputs_written) {
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for (unsigned j = 0; j < 4; j++) {
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nir_ssa_def *output = s->outputs[i][j];
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/* Next vertex emit need a new value, reset all outputs. */
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s->outputs[i][j] = NULL;
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if (!(s->info->usage_mask[i] & (1 << j)) ||
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((s->info->streams[i] >> (j * 2)) & 0x3) != stream)
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continue;
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unsigned base = offset * b->shader->info.gs.vertices_out;
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offset++;
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/* no one set this output, skip the buffer store */
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if (!output)
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continue;
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nir_ssa_def *voffset = nir_iadd_imm(b, vtxidx, base);
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voffset = nir_ishl_imm(b, voffset, 2);
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/* extend 8/16 bit to 32 bit, 64 bit has been lowered */
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nir_ssa_def *data = nir_u2uN(b, output, 32);
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nir_store_buffer_amd(b, data, gsvs_ring, voffset, soffset, nir_imm_int(b, 0),
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.is_swizzled = true, .slc_amd = true,
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.access = ACCESS_COHERENT,
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/* For ACO to not reorder this store around EmitVertex/EndPrimitve */
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.memory_modes = nir_var_shader_out);
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}
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}
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u_foreach_bit (i, b->shader->info.outputs_written_16bit) {
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for (unsigned j = 0; j < 4; j++) {
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nir_ssa_def *output_lo = s->outputs_16bit_lo[i][j];
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nir_ssa_def *output_hi = s->outputs_16bit_hi[i][j];
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/* Next vertex emit need a new value, reset all outputs. */
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s->outputs_16bit_lo[i][j] = NULL;
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s->outputs_16bit_hi[i][j] = NULL;
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bool has_lo_16bit = (s->info->usage_mask_16bit_lo[i] & (1 << j)) &&
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((s->info->streams_16bit_lo[i] >> (j * 2)) & 0x3) == stream;
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bool has_hi_16bit = (s->info->usage_mask_16bit_hi[i] & (1 << j)) &&
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((s->info->streams_16bit_hi[i] >> (j * 2)) & 0x3) == stream;
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if (!has_lo_16bit && !has_hi_16bit)
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continue;
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unsigned base = offset * b->shader->info.gs.vertices_out;
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offset++;
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bool has_lo_16bit_out = has_lo_16bit && output_lo;
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bool has_hi_16bit_out = has_hi_16bit && output_hi;
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/* no one set needed output, skip the buffer store */
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if (!has_lo_16bit_out && !has_hi_16bit_out)
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continue;
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if (!has_lo_16bit_out)
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output_lo = nir_ssa_undef(b, 1, 16);
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if (!has_hi_16bit_out)
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output_hi = nir_ssa_undef(b, 1, 16);
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nir_ssa_def *voffset = nir_iadd_imm(b, vtxidx, base);
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voffset = nir_ishl_imm(b, voffset, 2);
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nir_store_buffer_amd(b, nir_pack_32_2x16_split(b, output_lo, output_hi),
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gsvs_ring, voffset, soffset, nir_imm_int(b, 0),
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.is_swizzled = true, .slc_amd = true,
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.access = ACCESS_COHERENT,
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/* For ACO to not reorder this store around EmitVertex/EndPrimitve */
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.memory_modes = nir_var_shader_out);
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}
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}
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/* Keep this instruction to signal vertex emission. */
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return true;
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}
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static bool
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lower_legacy_gs_set_vertex_and_primitive_count(nir_builder *b, nir_intrinsic_instr *intrin,
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lower_legacy_gs_state *s)
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{
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b->cursor = nir_before_instr(&intrin->instr);
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unsigned stream = nir_intrinsic_stream_id(intrin);
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s->vertex_count[stream] = intrin->src[0].ssa;
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s->primitive_count[stream] = intrin->src[1].ssa;
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nir_instr_remove(&intrin->instr);
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return true;
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}
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static bool
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lower_legacy_gs_intrinsic(nir_builder *b, nir_instr *instr, void *state)
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{
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lower_legacy_gs_state *s = (lower_legacy_gs_state *) state;
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic == nir_intrinsic_store_output)
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return lower_legacy_gs_store_output(b, intrin, s);
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else if (intrin->intrinsic == nir_intrinsic_emit_vertex_with_counter)
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return lower_legacy_gs_emit_vertex_with_counter(b, intrin, s);
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else if (intrin->intrinsic == nir_intrinsic_set_vertex_and_primitive_count)
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return lower_legacy_gs_set_vertex_and_primitive_count(b, intrin, s);
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return false;
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}
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void
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ac_nir_lower_legacy_gs(nir_shader *nir,
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bool has_gen_prim_query,
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bool has_pipeline_stats_query,
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ac_nir_gs_output_info *output_info)
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{
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lower_legacy_gs_state s = {
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.info = output_info,
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};
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unsigned num_vertices_per_primitive = 0;
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switch (nir->info.gs.output_primitive) {
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case SHADER_PRIM_POINTS:
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num_vertices_per_primitive = 1;
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break;
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case SHADER_PRIM_LINE_STRIP:
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num_vertices_per_primitive = 2;
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break;
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case SHADER_PRIM_TRIANGLE_STRIP:
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num_vertices_per_primitive = 3;
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break;
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default:
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unreachable("Invalid GS output primitive.");
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break;
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}
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nir_shader_instructions_pass(nir, lower_legacy_gs_intrinsic,
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nir_metadata_block_index | nir_metadata_dominance, &s);
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nir_function_impl *impl = nir_shader_get_entrypoint(nir);
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nir_builder builder;
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nir_builder *b = &builder;
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nir_builder_init(b, impl);
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b->cursor = nir_after_cf_list(&impl->body);
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/* Emit shader query for mix use legacy/NGG GS */
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bool progress = ac_nir_gs_shader_query(b,
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has_gen_prim_query,
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has_pipeline_stats_query,
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num_vertices_per_primitive,
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64,
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s.vertex_count,
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s.primitive_count);
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if (progress)
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nir_metadata_preserve(impl, nir_metadata_none);
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}
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@@ -187,6 +187,16 @@ ac_nir_lower_global_access(nir_shader *shader);
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bool ac_nir_lower_resinfo(nir_shader *nir, enum amd_gfx_level gfx_level);
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typedef struct ac_nir_gs_output_info {
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const uint8_t *streams;
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const uint8_t *streams_16bit_lo;
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const uint8_t *streams_16bit_hi;
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const uint8_t *usage_mask;
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const uint8_t *usage_mask_16bit_lo;
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const uint8_t *usage_mask_16bit_hi;
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} ac_nir_gs_output_info;
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nir_shader *
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ac_nir_create_gs_copy_shader(const nir_shader *gs_nir,
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bool disable_streamout,
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@@ -207,6 +217,12 @@ ac_nir_gs_shader_query(nir_builder *b,
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nir_ssa_def *vertex_count[4],
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nir_ssa_def *primitive_count[4]);
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void
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ac_nir_lower_legacy_gs(nir_shader *nir,
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bool has_gen_prim_query,
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bool has_pipeline_stats_query,
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ac_nir_gs_output_info *output_info);
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#ifdef __cplusplus
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}
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#endif
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