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radv: move calculating primgroup_size to pipeline.

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This moves this out of the draw paths.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
2017-09-11 07:05:27 +01:00
parent 16eac0a756
commit d2490eb2d1
3 changed files with 11 additions and 9 deletions
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7
src/amd/vulkan/radv_pipeline.c
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@@ -2007,6 +2007,13 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
calculate_tess_state(pipeline, pCreateInfo); calculate_tess_state(pipeline, pCreateInfo);
} }
if (radv_pipeline_has_tess(pipeline))
pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
else if (radv_pipeline_has_gs(pipeline))
pipeline->graphics.primgroup_size = 64;
else
pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
const VkPipelineVertexInputStateCreateInfo *vi_info = const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState; pCreateInfo->pVertexInputState;
struct radv_vertex_elements_info *velems = &pipeline->vertex_elements; struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;

1
src/amd/vulkan/radv_private.h
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@@ -1075,6 +1075,7 @@ struct radv_pipeline {
uint32_t vgt_gs_mode; uint32_t vgt_gs_mode;
bool vgt_primitiveid_en; bool vgt_primitiveid_en;
bool prim_restart_enable; bool prim_restart_enable;
uint8_t primgroup_size;
unsigned esgs_ring_size; unsigned esgs_ring_size;
unsigned gsvs_ring_size; unsigned gsvs_ring_size;
uint32_t ps_input_cntl[32]; uint32_t ps_input_cntl[32];

12
src/amd/vulkan/si_cmd_buffer.c
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@@ -683,7 +683,6 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family; enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info; struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
unsigned prim = cmd_buffer->state.pipeline->graphics.prim; unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
unsigned primgroup_size = 128; /* recommended without a GS */
unsigned max_primgroup_in_wave = 2; unsigned max_primgroup_in_wave = 2;
/* SWITCH_ON_EOP(0) is always preferable. */ /* SWITCH_ON_EOP(0) is always preferable. */
bool wd_switch_on_eop = false; bool wd_switch_on_eop = false;
@@ -693,15 +692,10 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
bool partial_es_wave = false; bool partial_es_wave = false;
bool multi_instances_smaller_than_primgroup; bool multi_instances_smaller_than_primgroup;
if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
primgroup_size = cmd_buffer->state.pipeline->graphics.tess.num_patches;
else if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
primgroup_size = 64; /* recommended with a GS */
multi_instances_smaller_than_primgroup = indirect_draw; multi_instances_smaller_than_primgroup = indirect_draw;
if (!multi_instances_smaller_than_primgroup && instanced_draw) { if (!multi_instances_smaller_than_primgroup && instanced_draw) {
uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count); uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
if (num_prims < primgroup_size) if (num_prims < cmd_buffer->state.pipeline->graphics.primgroup_size)
multi_instances_smaller_than_primgroup = true; multi_instances_smaller_than_primgroup = true;
} }
@@ -803,7 +797,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
ia_switch_on_eoi = true; ia_switch_on_eoi = true;
/* GS requirement. */ /* GS requirement. */
if (SI_GS_PER_ES / primgroup_size >= cmd_buffer->device->gs_table_depth - 3) if (SI_GS_PER_ES / cmd_buffer->state.pipeline->graphics.primgroup_size >= cmd_buffer->device->gs_table_depth - 3)
partial_es_wave = true; partial_es_wave = true;
/* GS hw bug with single-primitive instances and SWITCH_ON_EOI. /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
@@ -826,7 +820,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) | S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) | S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) | S_028AA8_PRIMGROUP_SIZE(cmd_buffer->state.pipeline->graphics.primgroup_size - 1) |
S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) | S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) |
/* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */ /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class == VI ? S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class == VI ?