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broadcom/compiler: fix per-quad spilling

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This is not safe when we have conditional spills since we could be
spilling disabled lanes with undefined values that could overwrite
valid data for those lanes from a previous spill of the same temp
that was unconditional (or that condionally enabled those same
lanes).

Fixes some Piglit OpenCL tests as well as the following OpenCL tests:
integer_divideAssign
integer_moduloAssign
integer_mad_sat
integer_ops integer_divideAssign
integer_ops integer_mad_sat
integer_ops integer_moduloAssign
integer_ops quick_char_math
integer_ops quick_short_math
math_brute_force half_powr
math_brute_force pow
math_brute_force pown
math_brute_force powr
math_brute_force rootn

Fixes: 597560e27c ('broadcom/compiler: always enable per-quad on spill operations')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29909>
This commit is contained in:
Iago Toral Quiroga
2024-06-26 11:44:56 +02:00
committed by Marge Bot
parent 38b7f411a1
commit d1f8351f3c
1 changed files with 8 additions and 3 deletions
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11
src/broadcom/compiler/vir_register_allocate.c
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@@ -510,14 +510,19 @@ v3d_emit_spill_tmua(struct v3d_compile *c,
add_node(c, offset.index, get_class_bit_any(c->devinfo));
/* We always enable per-quad on spills/fills to ensure we spill
* any channels involved with helper invocations.
* any channels involved with helper invocations, but only if
* the spill is not conditional, since otherwise we may be spilling
* invalida lanes and overwriting valid data from a previous spill
* to the same address.
*/
struct qreg tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
struct qinst *inst = vir_ADD_dest(c, tmua, c->spill_base, offset);
inst->qpu.flags.ac = cond;
inst->ldtmu_count = 1;
inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
0xffffff7f); /* per-quad */
inst->uniform =
vir_get_uniform_index(c, QUNIFORM_CONSTANT,
cond != V3D_QPU_COND_NONE ?
0xffffffff : 0xffffff7f /* per-quad*/);
vir_emit_thrsw(c);