r300g: Use radeon compiler for fragment programs
This is entirely untested on R500, and needs more testing on R300.
This commit is contained in:
@@ -1,228 +0,0 @@
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/*
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* Copyright 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#include "r300_debug.h"
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static char* r5xx_fs_swiz[] = {
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" R",
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" G",
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" B",
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" A",
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" 0",
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".5",
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" 1",
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" U",
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};
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static char* r5xx_fs_op_rgb[] = {
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"MAD",
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"DP3",
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"DP4",
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"D2A",
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"MIN",
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"MAX",
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"---",
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"CND",
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"CMP",
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"FRC",
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"SOP",
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"MDH",
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"MDV",
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};
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static char* r5xx_fs_op_alpha[] = {
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"MAD",
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" DP",
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"MIN",
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"MAX",
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"---",
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"CND",
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"CMP",
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"FRC",
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"EX2",
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"LN2",
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"RCP",
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"RSQ",
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"SIN",
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"COS",
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"MDH",
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"MDV",
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};
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static char* r5xx_fs_mask[] = {
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"NONE",
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"R ",
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" G ",
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"RG ",
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" B ",
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"R B ",
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" GB ",
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"RGB ",
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" A",
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"R A",
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" G A",
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"RG A",
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" BA",
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"R BA",
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" GBA",
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"RGBA",
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};
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static char* r5xx_fs_tex[] = {
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" NOP",
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" LD",
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"TEXKILL",
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" PROJ",
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"LODBIAS",
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" LOD",
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" DXDY",
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};
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void r3xx_dump_fs(struct r3xx_fragment_shader* fs)
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{
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int i;
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for (i = 0; i < fs->alu_instruction_count; i++) {
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}
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}
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void r5xx_fs_dump(struct r5xx_fragment_shader* fs)
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{
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int i;
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uint32_t inst;
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for (i = 0; i < fs->instruction_count; i++) {
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inst = fs->instructions[i].inst0;
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debug_printf("%d: 0: CMN_INST 0x%08x:", i, inst);
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switch (inst & 0x3) {
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case R500_INST_TYPE_ALU:
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debug_printf("ALU ");
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break;
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case R500_INST_TYPE_OUT:
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debug_printf("OUT ");
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break;
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case R500_INST_TYPE_FC:
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debug_printf("FC ");
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break;
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case R500_INST_TYPE_TEX:
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debug_printf("TEX ");
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break;
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}
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debug_printf("%s %s %s %s ",
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inst & R500_INST_TEX_SEM_WAIT ? "TEX_WAIT" : "",
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inst & R500_INST_LAST ? "LAST" : "",
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inst & R500_INST_NOP ? "NOP" : "",
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inst & R500_INST_ALU_WAIT ? "ALU_WAIT" : "");
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debug_printf("wmask: %s omask: %s\n",
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r5xx_fs_mask[(inst >> 11) & 0xf],
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r5xx_fs_mask[(inst >> 15) & 0xf]);
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switch (inst & 0x3) {
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case R500_INST_TYPE_ALU:
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case R500_INST_TYPE_OUT:
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inst = fs->instructions[i].inst1;
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debug_printf(" 1: RGB_ADDR 0x%08x:", inst);
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debug_printf("Addr0: %d%c, Addr1: %d%c, "
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"Addr2: %d%c, srcp:%d\n",
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inst & 0xff, (inst & (1 << 8)) ? 'c' : 't',
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(inst >> 10) & 0xff, (inst & (1 << 18)) ? 'c' : 't',
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(inst >> 20) & 0xff, (inst & (1 << 28)) ? 'c' : 't',
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(inst >> 30));
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inst = fs->instructions[i].inst2;
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debug_printf(" 2: ALPHA_ADDR 0x%08x:", inst);
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debug_printf("Addr0: %d%c, Addr1: %d%c, "
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"Addr2: %d%c, srcp:%d\n",
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inst & 0xff, (inst & (1 << 8)) ? 'c' : 't',
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(inst >> 10) & 0xff, (inst & (1 << 18)) ? 'c' : 't',
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(inst >> 20) & 0xff, (inst & (1 << 28)) ? 'c' : 't',
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(inst >> 30));
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inst = fs->instructions[i].inst3;
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debug_printf(" 3: RGB_INST 0x%08x:", inst);
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debug_printf("rgb_A_src:%d %s/%s/%s %d "
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"rgb_B_src:%d %s/%s/%s %d\n",
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inst & 0x3, r5xx_fs_swiz[(inst >> 2) & 0x7],
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r5xx_fs_swiz[(inst >> 5) & 0x7],
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r5xx_fs_swiz[(inst >> 8) & 0x7],
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(inst >> 11) & 0x3, (inst >> 13) & 0x3,
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r5xx_fs_swiz[(inst >> 15) & 0x7],
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r5xx_fs_swiz[(inst >> 18) & 0x7],
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r5xx_fs_swiz[(inst >> 21) & 0x7],
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(inst >> 24) & 0x3);
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inst = fs->instructions[i].inst4;
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debug_printf(" 4: ALPHA_INST 0x%08x:", inst);
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debug_printf("%s dest:%d%s alp_A_src:%d %s %d "
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"alp_B_src:%d %s %d w:%d\n",
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r5xx_fs_op_alpha[inst & 0xf], (inst >> 4) & 0x7f,
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inst & (1<<11) ? "(rel)":"", (inst >> 12) & 0x3,
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r5xx_fs_swiz[(inst >> 14) & 0x7], (inst >> 17) & 0x3,
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(inst >> 19) & 0x3, r5xx_fs_swiz[(inst >> 21) & 0x7],
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(inst >> 24) & 0x3, (inst >> 31) & 0x1);
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inst = fs->instructions[i].inst5;
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debug_printf(" 5: RGBA_INST 0x%08x:", inst);
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debug_printf("%s dest:%d%s rgb_C_src:%d %s/%s/%s %d "
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"alp_C_src:%d %s %d\n",
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r5xx_fs_op_rgb[inst & 0xf], (inst >> 4) & 0x7f,
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inst & (1 << 11) ? "(rel)":"", (inst >> 12) & 0x3,
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r5xx_fs_swiz[(inst >> 14) & 0x7],
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r5xx_fs_swiz[(inst >> 17) & 0x7],
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r5xx_fs_swiz[(inst >> 20) & 0x7],
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(inst >> 23) & 0x3, (inst >> 25) & 0x3,
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r5xx_fs_swiz[(inst >> 27) & 0x7], (inst >> 30) & 0x3);
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break;
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case R500_INST_TYPE_FC:
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/* XXX don't even bother yet */
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break;
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case R500_INST_TYPE_TEX:
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inst = fs->instructions[i].inst1;
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debug_printf(" 1: TEX_INST 0x%08x: id: %d "
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"op:%s, %s, %s %s\n",
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inst, (inst >> 16) & 0xf,
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r5xx_fs_tex[(inst >> 22) & 0x7],
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(inst & (1 << 25)) ? "ACQ" : "",
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(inst & (1 << 26)) ? "IGNUNC" : "",
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(inst & (1 << 27)) ? "UNSCALED" : "SCALED");
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inst = fs->instructions[i].inst2;
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debug_printf(" 2: TEX_ADDR 0x%08x: "
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"src: %d%s %s/%s/%s/%s dst: %d%s %s/%s/%s/%s\n",
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inst, inst & 0x7f, inst & (1 << 7) ? "(rel)" : "",
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r5xx_fs_swiz[(inst >> 8) & 0x3],
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r5xx_fs_swiz[(inst >> 10) & 0x3],
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r5xx_fs_swiz[(inst >> 12) & 0x3],
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r5xx_fs_swiz[(inst >> 14) & 0x3],
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(inst >> 16) & 0x7f, inst & (1 << 23) ? "(rel)" : "",
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r5xx_fs_swiz[(inst >> 24) & 0x3],
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r5xx_fs_swiz[(inst >> 26) & 0x3],
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r5xx_fs_swiz[(inst >> 28) & 0x3],
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r5xx_fs_swiz[(inst >> 30) & 0x3]);
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inst = fs->instructions[i].inst3;
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debug_printf(" 3: TEX_DXDY 0x%08x\n", inst);
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break;
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}
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}
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}
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