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radv: move cs_regalloc_hang_bug to radv_shader_info

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This is more like a shader property.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22102>
This commit is contained in:
Samuel Pitoiset
2023-03-21 11:13:41 +01:00
committed by Marge Bot
parent 48ba17b823
commit d07c81d87e
5 changed files with 10 additions and 11 deletions
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5
src/amd/vulkan/radv_cmd_buffer.c
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@@ -9763,10 +9763,11 @@ static void
radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info, radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info,
struct radv_compute_pipeline *pipeline, VkPipelineBindPoint bind_point) struct radv_compute_pipeline *pipeline, VkPipelineBindPoint bind_point)
{ {
struct radv_shader *compute_shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
bool has_prefetch = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7; bool has_prefetch = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7;
bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline; bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline;
if (pipeline->cs_regalloc_hang_bug) if (compute_shader->info.cs.regalloc_hang_bug)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
RADV_CMD_FLAG_CS_PARTIAL_FLUSH; RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
@@ -9825,7 +9826,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf
: VK_PIPELINE_BIND_POINT_COMPUTE); : VK_PIPELINE_BIND_POINT_COMPUTE);
} }
if (pipeline->cs_regalloc_hang_bug) if (compute_shader->info.cs.regalloc_hang_bug)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH; cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH); radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);

7
src/amd/vulkan/radv_pipeline.c
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@@ -5303,13 +5303,6 @@ radv_compute_pipeline_init(struct radv_compute_pipeline *pipeline,
pipeline->base.shader_upload_seq = pipeline->base.shaders[MESA_SHADER_COMPUTE]->upload_seq; pipeline->base.shader_upload_seq = pipeline->base.shaders[MESA_SHADER_COMPUTE]->upload_seq;
if (device->physical_device->rad_info.has_cs_regalloc_hang_bug) {
struct radv_shader *compute_shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
unsigned *cs_block_size = compute_shader->info.cs.block_size;
pipeline->cs_regalloc_hang_bug = cs_block_size[0] * cs_block_size[1] * cs_block_size[2] > 256;
}
radv_compute_generate_pm4(pipeline); radv_compute_generate_pm4(pipeline);
} }

2
src/amd/vulkan/radv_private.h
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@@ -2275,8 +2275,6 @@ struct radv_graphics_pipeline {
struct radv_compute_pipeline { struct radv_compute_pipeline {
struct radv_pipeline base; struct radv_pipeline base;
bool cs_regalloc_hang_bug;
}; };
struct radv_ray_tracing_module { struct radv_ray_tracing_module {

2
src/amd/vulkan/radv_shader.h
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@@ -367,6 +367,8 @@ struct radv_shader_info {
bool uses_dynamic_rt_callable_stack; bool uses_dynamic_rt_callable_stack;
bool uses_rt; bool uses_rt;
bool uses_full_subgroups; bool uses_full_subgroups;
bool regalloc_hang_bug;
} cs; } cs;
struct { struct {
uint64_t tes_inputs_read; uint64_t tes_inputs_read;

5
src/amd/vulkan/radv_shader_info.c
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@@ -697,6 +697,11 @@ gather_shader_info_cs(struct radv_device *device, const nir_shader *nir,
} }
info->cs.subgroup_size = subgroup_size; info->cs.subgroup_size = subgroup_size;
if (device->physical_device->rad_info.has_cs_regalloc_hang_bug) {
info->cs.regalloc_hang_bug =
info->cs.block_size[0] * info->cs.block_size[1] * info->cs.block_size[2] > 256;
}
} }
static void static void