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intel/dev: switch defect identifiers to use lineage numbers

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Update existing workarounds when necessary to match changed
identifiers.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23226>
This commit is contained in:
Mark Janes
2023-05-24 13:52:15 -07:00
committed by Marge Bot
parent b94d35f74d
commit d0669f3ede
9 changed files with 1245 additions and 1160 deletions
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38
src/gallium/drivers/iris/iris_state.c
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@@ -4862,9 +4862,9 @@ iris_store_tes_state(const struct intel_device_info *devinfo,
te.MaximumTessellationFactorNotOdd = 64.0; te.MaximumTessellationFactorNotOdd = 64.0;
#if GFX_VERx10 >= 125 #if GFX_VERx10 >= 125
STATIC_ASSERT(TEDMODE_OFF == 0); STATIC_ASSERT(TEDMODE_OFF == 0);
if (intel_needs_workaround(devinfo, 14015297576)) { if (intel_needs_workaround(devinfo, 14015055625)) {
te.TessellationDistributionMode = TEDMODE_OFF; te.TessellationDistributionMode = TEDMODE_OFF;
} else if (intel_needs_workaround(devinfo, 22012785325)) { } else if (intel_needs_workaround(devinfo, 22012699309)) {
te.TessellationDistributionMode = TEDMODE_RR_STRICT; te.TessellationDistributionMode = TEDMODE_RR_STRICT;
} else { } else {
te.TessellationDistributionMode = TEDMODE_RR_FREE; te.TessellationDistributionMode = TEDMODE_RR_FREE;
@@ -6133,24 +6133,24 @@ iris_preemption_streamout_wa(struct iris_context *ice,
} }
static void static void
shader_program_needs_wa_14015297576(struct iris_context *ice, shader_program_needs_wa_14015055625(struct iris_context *ice,
struct iris_batch *batch, struct iris_batch *batch,
const struct brw_stage_prog_data *prog_data, const struct brw_stage_prog_data *prog_data,
gl_shader_stage stage, gl_shader_stage stage,
bool *program_needs_wa_14015297576) bool *program_needs_wa_14015055625)
{ {
if (!intel_needs_workaround(batch->screen->devinfo, 14015297576)) if (!intel_needs_workaround(batch->screen->devinfo, 14015055625))
return; return;
switch (stage) { switch (stage) {
case MESA_SHADER_TESS_CTRL: { case MESA_SHADER_TESS_CTRL: {
struct brw_tcs_prog_data *tcs_prog_data = (void *) prog_data; struct brw_tcs_prog_data *tcs_prog_data = (void *) prog_data;
*program_needs_wa_14015297576 |= tcs_prog_data->include_primitive_id; *program_needs_wa_14015055625 |= tcs_prog_data->include_primitive_id;
break; break;
} }
case MESA_SHADER_TESS_EVAL: { case MESA_SHADER_TESS_EVAL: {
struct brw_tes_prog_data *tes_prog_data = (void *) prog_data; struct brw_tes_prog_data *tes_prog_data = (void *) prog_data;
*program_needs_wa_14015297576 |= tes_prog_data->include_primitive_id; *program_needs_wa_14015055625 |= tes_prog_data->include_primitive_id;
break; break;
} }
default: default:
@@ -6162,7 +6162,7 @@ shader_program_needs_wa_14015297576(struct iris_context *ice,
const struct brw_gs_prog_data *gs_prog_data = const struct brw_gs_prog_data *gs_prog_data =
gs_shader ? (void *) gs_shader->prog_data : NULL; gs_shader ? (void *) gs_shader->prog_data : NULL;
*program_needs_wa_14015297576 |= *program_needs_wa_14015055625 |=
gs_prog_data && gs_prog_data->include_primitive_id; gs_prog_data && gs_prog_data->include_primitive_id;
} }
@@ -6508,14 +6508,14 @@ iris_upload_dirty_render_state(struct iris_context *ice,
} }
} }
bool program_needs_wa_14015297576 = false; bool program_needs_wa_14015055625 = false;
/* Check if FS stage will use primitive ID overrides for Wa_14015297576. */ /* Check if FS stage will use primitive ID overrides for Wa_14015055625. */
const struct brw_vue_map *last_vue_map = const struct brw_vue_map *last_vue_map =
&brw_vue_prog_data(ice->shaders.last_vue_shader->prog_data)->vue_map; &brw_vue_prog_data(ice->shaders.last_vue_shader->prog_data)->vue_map;
if ((wm_prog_data->inputs & VARYING_BIT_PRIMITIVE_ID) && if ((wm_prog_data->inputs & VARYING_BIT_PRIMITIVE_ID) &&
last_vue_map->varying_to_slot[VARYING_SLOT_PRIMITIVE_ID] == -1) { last_vue_map->varying_to_slot[VARYING_SLOT_PRIMITIVE_ID] == -1) {
program_needs_wa_14015297576 = true; program_needs_wa_14015055625 = true;
} }
for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) { for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
@@ -6532,8 +6532,8 @@ iris_upload_dirty_render_state(struct iris_context *ice,
uint32_t scratch_addr = uint32_t scratch_addr =
pin_scratch_space(ice, batch, prog_data, stage); pin_scratch_space(ice, batch, prog_data, stage);
shader_program_needs_wa_14015297576(ice, batch, prog_data, stage, shader_program_needs_wa_14015055625(ice, batch, prog_data, stage,
&program_needs_wa_14015297576); &program_needs_wa_14015055625);
if (stage == MESA_SHADER_FRAGMENT) { if (stage == MESA_SHADER_FRAGMENT) {
UNUSED struct iris_rasterizer_state *cso = ice->state.cso_rast; UNUSED struct iris_rasterizer_state *cso = ice->state.cso_rast;
@@ -6592,15 +6592,15 @@ iris_upload_dirty_render_state(struct iris_context *ice,
iris_emit_merge(batch, shader_psx, psx_state, iris_emit_merge(batch, shader_psx, psx_state,
GENX(3DSTATE_PS_EXTRA_length)); GENX(3DSTATE_PS_EXTRA_length));
} else if (stage == MESA_SHADER_TESS_EVAL && } else if (stage == MESA_SHADER_TESS_EVAL &&
intel_needs_workaround(batch->screen->devinfo, 14015297576) && intel_needs_workaround(batch->screen->devinfo, 14015055625) &&
!program_needs_wa_14015297576) { !program_needs_wa_14015055625) {
/* This program doesn't require Wa_14015297576, so we can enable /* This program doesn't require Wa_14015055625, so we can enable
* a Tessellation Distribution Mode. * a Tessellation Distribution Mode.
*/ */
#if GFX_VERx10 >= 125 #if GFX_VERx10 >= 125
uint32_t te_state[GENX(3DSTATE_TE_length)] = { 0 }; uint32_t te_state[GENX(3DSTATE_TE_length)] = { 0 };
iris_pack_command(GENX(3DSTATE_TE), te_state, te) { iris_pack_command(GENX(3DSTATE_TE), te_state, te) {
if (intel_needs_workaround(batch->screen->devinfo, 22012785325)) if (intel_needs_workaround(batch->screen->devinfo, 22012699309))
te.TessellationDistributionMode = TEDMODE_RR_STRICT; te.TessellationDistributionMode = TEDMODE_RR_STRICT;
else else
te.TessellationDistributionMode = TEDMODE_RR_FREE; te.TessellationDistributionMode = TEDMODE_RR_FREE;
@@ -7415,11 +7415,11 @@ iris_upload_render_state(struct iris_context *ice,
batch->contains_draw_with_next_seqno = true; batch->contains_draw_with_next_seqno = true;
} }
/* Wa_1409433168 - Send HS state for every primitive on gfx11. /* Wa_1306463417 - Send HS state for every primitive on gfx11.
* Wa_16011107343 (same for gfx12) * Wa_16011107343 (same for gfx12)
* We implement this by setting TCS dirty on each draw. * We implement this by setting TCS dirty on each draw.
*/ */
if ((INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343) && if ((INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343) &&
ice->shaders.prog[MESA_SHADER_TESS_CTRL]) { ice->shaders.prog[MESA_SHADER_TESS_CTRL]) {
ice->state.stage_dirty |= IRIS_STAGE_DIRTY_TCS; ice->state.stage_dirty |= IRIS_STAGE_DIRTY_TCS;
} }

2
src/intel/common/intel_genX_state.h
View File

@@ -131,7 +131,7 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
UNUSED static int UNUSED static int
preferred_slm_allocation_size(const struct intel_device_info *devinfo) preferred_slm_allocation_size(const struct intel_device_info *devinfo)
{ {
if (intel_needs_workaround(devinfo, 14017341140)) if (intel_needs_workaround(devinfo, 14017245111))
return SLM_ENCODES_96K; return SLM_ENCODES_96K;
return 0; return 0;

4
src/intel/compiler/brw_nir.c
View File

@@ -1101,7 +1101,7 @@ brw_nir_zero_inputs(nir_shader *shader, uint64_t *zero_inputs)
nir_metadata_block_index | nir_metadata_dominance, zero_inputs); nir_metadata_block_index | nir_metadata_dominance, zero_inputs);
} }
/* Code for Wa_14015590813 may have created input/output variables beyond /* Code for Wa_18019110168 may have created input/output variables beyond
* VARYING_SLOT_MAX and removed uses of variables below VARYING_SLOT_MAX. * VARYING_SLOT_MAX and removed uses of variables below VARYING_SLOT_MAX.
* Clean it up, so they all stay below VARYING_SLOT_MAX. * Clean it up, so they all stay below VARYING_SLOT_MAX.
*/ */
@@ -1138,7 +1138,7 @@ brw_mesh_compact_io(nir_shader *mesh, nir_shader *frag)
if (!compact) if (!compact)
return; return;
/* The rest of this function should be hit only for Wa_14015590813. */ /* The rest of this function should be hit only for Wa_18019110168. */
nir_foreach_shader_out_variable(var, mesh) { nir_foreach_shader_out_variable(var, mesh) {
gl_varying_slot location = var->data.location; gl_varying_slot location = var->data.location;

2
src/intel/dev/intel_device_info.c
View File

@@ -1373,7 +1373,7 @@ intel_device_info_init_common(int pci_id,
static void static void
intel_device_info_apply_workarounds(struct intel_device_info *devinfo) intel_device_info_apply_workarounds(struct intel_device_info *devinfo)
{ {
if (intel_needs_workaround(devinfo, 22012575642)) if (intel_needs_workaround(devinfo, 18012660806))
devinfo->urb.max_entries[MESA_SHADER_GEOMETRY] = 1536; devinfo->urb.max_entries[MESA_SHADER_GEOMETRY] = 1536;
/* Fixes issues with: /* Fixes issues with:

2321
src/intel/dev/mesa_defs.json
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File diff suppressed because it is too large Load Diff

4
src/intel/vulkan/anv_image.c
View File

@@ -345,7 +345,7 @@ can_fast_clear_with_non_zero_color(const struct intel_device_info *devinfo,
return false; return false;
/* On TGL (< C0), if a block of fragment shader outputs match the surface's /* On TGL (< C0), if a block of fragment shader outputs match the surface's
* clear color, the HW may convert them to fast-clears (see HSD 14010672564). * clear color, the HW may convert them to fast-clears (see HSD 1607794140).
* This can lead to rendering corruptions if not handled properly. We * This can lead to rendering corruptions if not handled properly. We
* restrict the clear color to zero to avoid issues that can occur with: * restrict the clear color to zero to avoid issues that can occur with:
* - Texture view rendering (including blorp_copy calls) * - Texture view rendering (including blorp_copy calls)
@@ -757,7 +757,7 @@ add_aux_surface_if_supported(struct anv_device *device,
image->vk.format, image->vk.tiling, image->vk.format, image->vk.tiling,
image->vk.usage, fmt_list)) { image->vk.usage, fmt_list)) {
image->planes[plane].aux_usage = image->planes[plane].aux_usage =
intel_needs_workaround(device->info, 14010672564) ? intel_needs_workaround(device->info, 1607794140) ?
ISL_AUX_USAGE_GFX12_CCS_E : ISL_AUX_USAGE_GFX12_CCS_E :
ISL_AUX_USAGE_CCS_E; ISL_AUX_USAGE_CCS_E;
} else if (device->info->ver >= 12) { } else if (device->info->ver >= 12) {

4
src/intel/vulkan/anv_mesh_perprim_wa.c
View File

@@ -25,7 +25,7 @@
#include "nir_builder.h" #include "nir_builder.h"
/* /*
* Wa_14015590813 for gfx 12.5. * Wa_18019110168 for gfx 12.5.
* *
* This file implements workaround for HW bug, which leads to fragment shader * This file implements workaround for HW bug, which leads to fragment shader
* reading incorrect per-primitive data if mesh shader, in addition to writing * reading incorrect per-primitive data if mesh shader, in addition to writing
@@ -532,7 +532,7 @@ anv_apply_per_prim_attr_wa(struct nir_shader *ms_nir,
int mesh_conv_prim_attrs_to_vert_attrs = int mesh_conv_prim_attrs_to_vert_attrs =
device->physical->instance->mesh_conv_prim_attrs_to_vert_attrs; device->physical->instance->mesh_conv_prim_attrs_to_vert_attrs;
if (mesh_conv_prim_attrs_to_vert_attrs < 0 && if (mesh_conv_prim_attrs_to_vert_attrs < 0 &&
!intel_needs_workaround(devinfo, 14015590813)) !intel_needs_workaround(devinfo, 18019110168))
mesh_conv_prim_attrs_to_vert_attrs = 0; mesh_conv_prim_attrs_to_vert_attrs = 0;
if (mesh_conv_prim_attrs_to_vert_attrs != 0) { if (mesh_conv_prim_attrs_to_vert_attrs != 0) {

24
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -3420,9 +3420,9 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->state.push_descriptors_dirty &= ~push_descriptor_dirty; cmd_buffer->state.push_descriptors_dirty &= ~push_descriptor_dirty;
} }
/* Wa_1409433168, Wa_16011107343 - Send HS state for every primitive. */ /* Wa_1306463417, Wa_16011107343 - Send HS state for every primitive. */
if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE || if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE ||
(INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343)) { (INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343)) {
genX(emit_hs)(cmd_buffer); genX(emit_hs)(cmd_buffer);
} }
@@ -3586,9 +3586,9 @@ anv_use_generated_draws(const struct anv_cmd_buffer *cmd_buffer, uint32_t count)
const struct anv_device *device = cmd_buffer->device; const struct anv_device *device = cmd_buffer->device;
/* Limit generated draws to pipelines without HS stage. This makes things /* Limit generated draws to pipelines without HS stage. This makes things
* simpler for implementing Wa_1409433168, Wa_16011107343. * simpler for implementing Wa_1306463417, Wa_16011107343.
*/ */
if ((INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343) && if ((INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343) &&
anv_pipeline_has_stage(cmd_buffer->state.gfx.pipeline, anv_pipeline_has_stage(cmd_buffer->state.gfx.pipeline,
MESA_SHADER_TESS_CTRL)) { MESA_SHADER_TESS_CTRL)) {
return false; return false;
@@ -4269,10 +4269,10 @@ void genX(CmdDrawMultiEXT)(
#else #else
vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride) { vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride) {
/* Wa_1409433168, Wa_16011107343 - Send HS state for every primitive, /* Wa_1306463417, Wa_16011107343 - Send HS state for every primitive,
* first one was handled by cmd_buffer_flush_gfx_state. * first one was handled by cmd_buffer_flush_gfx_state.
*/ */
if (i && (INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343)) if (i && (INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343))
genX(emit_hs)(cmd_buffer); genX(emit_hs)(cmd_buffer);
const uint32_t count = draw->vertexCount * instanceCount; const uint32_t count = draw->vertexCount * instanceCount;
@@ -4502,10 +4502,10 @@ void genX(CmdDrawMultiIndexedEXT)(
#else #else
vk_foreach_multi_draw_indexed(draw, i, pIndexInfo, drawCount, stride) { vk_foreach_multi_draw_indexed(draw, i, pIndexInfo, drawCount, stride) {
/* Wa_1409433168, Wa_16011107343 - Send HS state for every primitive, /* Wa_1306463417, Wa_16011107343 - Send HS state for every primitive,
* first one was handled by cmd_buffer_flush_gfx_state. * first one was handled by cmd_buffer_flush_gfx_state.
*/ */
if (i && (INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343)) if (i && (INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343))
genX(emit_hs)(cmd_buffer); genX(emit_hs)(cmd_buffer);
const uint32_t count = const uint32_t count =
@@ -4761,10 +4761,10 @@ emit_indirect_draws(struct anv_cmd_buffer *cmd_buffer,
load_indirect_parameters(cmd_buffer, draw, indexed, i); load_indirect_parameters(cmd_buffer, draw, indexed, i);
/* Wa_1409433168, Wa_16011107343 - Send HS state for every primitive, /* Wa_1306463417, Wa_16011107343 - Send HS state for every primitive,
* first one was handled by cmd_buffer_flush_gfx_state. * first one was handled by cmd_buffer_flush_gfx_state.
*/ */
if (i && (INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343)) if (i && (INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343))
genX(emit_hs)(cmd_buffer); genX(emit_hs)(cmd_buffer);
anv_batch_emit(&cmd_buffer->batch, anv_batch_emit(&cmd_buffer->batch,
@@ -4986,10 +4986,10 @@ emit_indirect_count_draws(struct anv_cmd_buffer *cmd_buffer,
load_indirect_parameters(cmd_buffer, draw, indexed, i); load_indirect_parameters(cmd_buffer, draw, indexed, i);
/* Wa_1409433168, Wa_16011107343 - Send HS state for every primitive, /* Wa_1306463417, Wa_16011107343 - Send HS state for every primitive,
* first one was handled by cmd_buffer_flush_gfx_state. * first one was handled by cmd_buffer_flush_gfx_state.
*/ */
if (i && (INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343)) if (i && (INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343))
genX(emit_hs)(cmd_buffer); genX(emit_hs)(cmd_buffer);
anv_batch_emit(&cmd_buffer->batch, anv_batch_emit(&cmd_buffer->batch,

6
src/intel/vulkan/gfx8_cmd_buffer.c
View File

@@ -250,13 +250,13 @@ genX(cmd_emit_te)(struct anv_cmd_buffer *cmd_buffer)
te.MaximumTessellationFactorOdd = 63.0; te.MaximumTessellationFactorOdd = 63.0;
te.MaximumTessellationFactorNotOdd = 64.0; te.MaximumTessellationFactorNotOdd = 64.0;
#if GFX_VERx10 >= 125 #if GFX_VERx10 >= 125
if (intel_needs_workaround(cmd_buffer->device->info, 22012785325)) if (intel_needs_workaround(cmd_buffer->device->info, 22012699309))
te.TessellationDistributionMode = TEDMODE_RR_STRICT; te.TessellationDistributionMode = TEDMODE_RR_STRICT;
else else
te.TessellationDistributionMode = TEDMODE_RR_FREE; te.TessellationDistributionMode = TEDMODE_RR_FREE;
if (intel_needs_workaround(cmd_buffer->device->info, 14015297576)) { if (intel_needs_workaround(cmd_buffer->device->info, 14015055625)) {
/* Wa_14015297576: /* Wa_14015055625:
* *
* Disable Tessellation Distribution when primitive Id is enabled. * Disable Tessellation Distribution when primitive Id is enabled.
*/ */