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intel/compiler: use shader source hash in shader dump code

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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23942>
This commit is contained in:
Felix DeGrood
2023-07-18 18:48:48 +00:00
committed by Marge Bot
parent 6ac8a9a030
commit d04be9770b
5 changed files with 25 additions and 7 deletions
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2
src/intel/compiler/brw_compiler.h
View File

@@ -1766,6 +1766,8 @@ struct brw_compile_params {
char *error_str;
uint64_t debug_flag;
uint32_t source_hash;
};
/**

4
src/intel/compiler/brw_fs_generator.cpp
View File

@@ -2388,13 +2388,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
after_size, sha1);
_mesa_sha1_format(sha1buf, sha1);
fprintf(stderr, "Native code for %s (sha1 %s)\n"
fprintf(stderr, "Native code for %s (src_hash 0x%08x) (sha1 %s)\n"
"SIMD%d shader: %d instructions. %d loops. %u cycles. "
"%d:%d spills:fills, %u sends, "
"scheduled with mode %s. "
"Promoted %u constants. "
"Compacted %d to %d bytes (%.0f%%)\n",
shader_name, sha1buf,
shader_name, params->source_hash, sha1buf,
dispatch_width, before_size / 16,
loop_count, perf.latency,
shader_stats.spill_count,

10
src/intel/compiler/brw_vec4_generator.cpp
View File

@@ -1513,7 +1513,7 @@ generate_zero_oob_push_regs(struct brw_codegen *p,
static void
generate_code(struct brw_codegen *p,
const struct brw_compiler *compiler,
void *log_data,
const struct brw_compile_params *params,
const nir_shader *nir,
struct brw_vue_prog_data *prog_data,
const struct cfg_t *cfg,
@@ -2238,10 +2238,10 @@ generate_code(struct brw_codegen *p,
_mesa_sha1_compute(p->store, p->next_insn_offset, sha1);
_mesa_sha1_format(sha1buf, sha1);
fprintf(stderr, "Native code for %s %s shader %s (sha1 %s):\n",
fprintf(stderr, "Native code for %s %s shader %s (src_hash 0x%08x) (sha1 %s):\n",
nir->info.label ? nir->info.label : "unnamed",
_mesa_shader_stage_to_string(nir->info.stage), nir->info.name,
sha1buf);
params->source_hash, sha1buf);
fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
"spills:fills, %u sends. Compacted %d to %d bytes (%.0f%%)\n",
@@ -2260,7 +2260,7 @@ generate_code(struct brw_codegen *p,
ralloc_free(disasm_info);
assert(validated);
brw_shader_debug_log(compiler, log_data,
brw_shader_debug_log(compiler, params->log_data,
"%s vec4 shader: %d inst, %d loops, %u cycles, "
"%d:%d spills:fills, %u sends, "
"compacted %d to %d bytes.\n",
@@ -2292,7 +2292,7 @@ brw_vec4_generate_assembly(const struct brw_compiler *compiler,
brw_init_codegen(&compiler->isa, p, params->mem_ctx);
brw_set_default_access_mode(p, BRW_ALIGN_16);
generate_code(p, compiler, params->log_data,
generate_code(p, compiler, params,
nir, prog_data, cfg, perf,
params->stats, debug_enabled);