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gallium: rework vbuf alignment pipe caps

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this consolidates 4 pipe caps into 1 using an enum

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Neha Bhende <neha.bhende@broadcom.com>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31482>
This commit is contained in:
Mike Blumenkrantz
2024-10-02 06:26:32 -04:00
committed by Marge Bot
parent afe28429f9
commit d008aaa6da
17 changed files with 66 additions and 77 deletions
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24
docs/gallium/screen.rst
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@@ -128,21 +128,19 @@ The integer capabilities:
buffers. If not, gallium frontends must upload all data which is not in HW
resources. If user-space buffers are supported, the driver must also still
accept HW resource buffers.
* ``PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY``: This CAP describes a HW
limitation. If true, pipe_vertex_buffer::buffer_offset must always be aligned
to 4. If false, there are no restrictions on the offset.
* ``PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY``: This CAP describes a HW
limitation. If true, pipe_vertex_buffer::stride must always be aligned to 4.
If false, there are no restrictions on the stride.
* ``PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY``: This CAP describes
a HW limitation. If true, pipe_vertex_element::src_offset must always be
aligned to 4. If false, there are no restrictions on src_offset.
* ``PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY``: This CAP describes
a HW limitation. If true, the sum of
* ``PIPE_CAP_VERTEX_INPUT_ALIGNMENT``: This CAP describes a HW
limitation.
If ``PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE```,
pipe_vertex_buffer::buffer_offset must always be aligned
to 4, and pipe_vertex_buffer::stride must always be aligned to 4,
and pipe_vertex_element::src_offset must always be
aligned to 4.
If ``PIPE_VERTEX_INPUT_ALIGNMENT_ELEMENT``,
the sum of
``pipe_vertex_element::src_offset + pipe_vertex_buffer::buffer_offset + pipe_vertex_buffer::stride``
must always be aligned to the component size for the vertex attributes
which access that buffer. If false, there are no restrictions on these values.
This CAP cannot be used with any other alignment-requiring CAPs.
which access that buffer.
If ``PIPE_VERTEX_INPUT_ALIGNMENT_NONE``, there are no restrictions on these values.
* ``PIPE_CAP_COMPUTE``: Whether the implementation supports the
compute entry points defined in pipe_context and pipe_screen.
* ``PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT``: Describes the required