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gallium: rework vbuf alignment pipe caps

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this consolidates 4 pipe caps into 1 using an enum

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Neha Bhende <neha.bhende@broadcom.com>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31482>
This commit is contained in:
Mike Blumenkrantz
2024-10-02 06:26:32 -04:00
committed by Marge Bot
parent afe28429f9
commit d008aaa6da
17 changed files with 66 additions and 77 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
docs/gallium/screen.rst
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@@ -128,21 +128,19 @@ The integer capabilities:
buffers. If not, gallium frontends must upload all data which is not in HW
resources. If user-space buffers are supported, the driver must also still
accept HW resource buffers.
* ``PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY``: This CAP describes a HW
limitation. If true, pipe_vertex_buffer::buffer_offset must always be aligned
to 4. If false, there are no restrictions on the offset.
* ``PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY``: This CAP describes a HW
limitation. If true, pipe_vertex_buffer::stride must always be aligned to 4.
If false, there are no restrictions on the stride.
* ``PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY``: This CAP describes
a HW limitation. If true, pipe_vertex_element::src_offset must always be
aligned to 4. If false, there are no restrictions on src_offset.
* ``PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY``: This CAP describes
a HW limitation. If true, the sum of
* ``PIPE_CAP_VERTEX_INPUT_ALIGNMENT``: This CAP describes a HW
limitation.
If ``PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE```,
pipe_vertex_buffer::buffer_offset must always be aligned
to 4, and pipe_vertex_buffer::stride must always be aligned to 4,
and pipe_vertex_element::src_offset must always be
aligned to 4.
If ``PIPE_VERTEX_INPUT_ALIGNMENT_ELEMENT``,
the sum of
``pipe_vertex_element::src_offset + pipe_vertex_buffer::buffer_offset + pipe_vertex_buffer::stride``
must always be aligned to the component size for the vertex attributes
which access that buffer. If false, there are no restrictions on these values.
This CAP cannot be used with any other alignment-requiring CAPs.
which access that buffer.
If ``PIPE_VERTEX_INPUT_ALIGNMENT_NONE``, there are no restrictions on these values.
* ``PIPE_CAP_COMPUTE``: Whether the implementation supports the
compute entry points defined in pipe_context and pipe_screen.
* ``PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT``: Describes the required

4
src/gallium/auxiliary/gallivm/lp_bld_gather.c
View File

@@ -105,7 +105,7 @@ lp_build_gather_elem(struct gallivm_state *gallivm,
* two >= 32). On x86 it doesn't matter, however.
* We should be able to guarantee full alignment for any kind of texture
* fetch (except ARB_texture_buffer_range, oops), but not vertex fetch
* (there's PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY and friends
* (there's PIPE_CAP_VERTEX_INPUT_ALIGNMENT
* but I don't think that's quite what we wanted).
* For ARB_texture_buffer_range, PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
* looks like a good fit, but it seems this cap bit (and OpenGL) aren't
@@ -185,7 +185,7 @@ lp_build_gather_elem_vec(struct gallivm_state *gallivm,
* two >= 32). On x86 it doesn't matter, however.
* We should be able to guarantee full alignment for any kind of texture
* fetch (except ARB_texture_buffer_range, oops), but not vertex fetch
* (there's PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY and friends
* (there's PIPE_CAP_VERTEX_INPUT_ALIGNMENT
* but I don't think that's quite what we wanted).
* For ARB_texture_buffer_range, PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
* looks like a good fit, but it seems this cap bit (and OpenGL) aren't

7
src/gallium/auxiliary/util/u_screen.c
View File

@@ -140,13 +140,12 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_USER_VERTEX_BUFFERS:
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY:
case PIPE_CAP_COMPUTE:
return 0;
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return PIPE_VERTEX_INPUT_ALIGNMENT_NONE;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
/* GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT default value. */
return 1;

34
src/gallium/auxiliary/util/u_vbuf.c
View File

@@ -305,20 +305,26 @@ void u_vbuf_get_caps(struct pipe_screen *screen, struct u_vbuf_caps *caps,
}
}
caps->buffer_offset_unaligned =
!screen->get_param(screen,
PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY);
caps->buffer_stride_unaligned =
!screen->get_param(screen,
PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY);
caps->velem_src_offset_unaligned =
!screen->get_param(screen,
PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY);
caps->attrib_component_unaligned =
!screen->get_param(screen,
PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY);
assert(caps->attrib_component_unaligned ||
(caps->velem_src_offset_unaligned && caps->buffer_stride_unaligned && caps->buffer_offset_unaligned));
/* by default, all of these are supported */
caps->velem_src_offset_unaligned = 1;
caps->buffer_stride_unaligned = 1;
caps->buffer_offset_unaligned = 1;
caps->attrib_component_unaligned = 1;
/* pipe cap removes capabilities */
switch (screen->get_param(screen, PIPE_CAP_VERTEX_INPUT_ALIGNMENT)) {
case PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE:
caps->velem_src_offset_unaligned = 0;
caps->buffer_stride_unaligned = 0;
caps->buffer_offset_unaligned = 0;
break;
case PIPE_VERTEX_INPUT_ALIGNMENT_ELEMENT:
caps->attrib_component_unaligned = 0;
break;
default:
break;
}
caps->user_vertex_buffers =
screen->get_param(screen, PIPE_CAP_USER_VERTEX_BUFFERS);
caps->max_vertex_buffers =

4
src/gallium/drivers/asahi/agx_pipe.c
View File

@@ -2091,8 +2091,8 @@ agx_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 64;
case PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY:
return 1;
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return PIPE_VERTEX_INPUT_ALIGNMENT_ELEMENT;
case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
return true;

5
src/gallium/drivers/d3d12/d3d12_screen.cpp
View File

@@ -176,10 +176,12 @@ d3d12_get_param_default(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
return 1;
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE;
/* We need to do some lowering that requires a link to the sampler */
case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
return 1;
@@ -286,7 +288,6 @@ d3d12_get_param_default(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
case PIPE_CAP_QUERY_TIMESTAMP:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_IMAGE_STORE_FORMATTED:
case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
return 1;

5
src/gallium/drivers/etnaviv/etnaviv_screen.c
View File

@@ -162,9 +162,6 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
case PIPE_CAP_TEXTURE_BARRIER:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
@@ -172,6 +169,8 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_FRONTEND_NOOP:
return 1;
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE;
case PIPE_CAP_NATIVE_FENCE_FD:
return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
case PIPE_CAP_FS_POSITION_IS_SYSVAL:

6
src/gallium/drivers/freedreno/freedreno_screen.c
View File

@@ -239,10 +239,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_DEPTH_BOUNDS_TEST:
return is_a6xx(screen);
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
return is_a2xx(screen);
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return is_a2xx(screen) ? PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE : PIPE_VERTEX_INPUT_ALIGNMENT_NONE;
case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
return is_a2xx(screen);

5
src/gallium/drivers/nouveau/nv30/nv30_screen.c
View File

@@ -97,12 +97,11 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_CLEAR_SCISSORED:
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_QUERY_MEMORY_INFO:
return 1;
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE;
case PIPE_CAP_TEXTURE_TRANSFER_MODES:
return PIPE_TEXTURE_TRANSFER_BLIT;
/* nv35 capabilities */

6
src/gallium/drivers/panfrost/pan_screen.c
View File

@@ -258,11 +258,11 @@ panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
* require element alignment for vertex buffers, using u_vbuf to
* translate to match the hardware requirement.
*
* This is less heavy-handed than the 4BYTE_ALIGNED_ONLY caps, which
* This is less heavy-handed than PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE, which
* would needlessly require alignment even for 8-bit formats.
*/
case PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY:
return 1;
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return PIPE_VERTEX_INPUT_ALIGNMENT_ELEMENT;
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
return 1 << (PAN_MAX_MIP_LEVELS - 1);

6
src/gallium/drivers/r300/r300_screen.c
View File

@@ -177,10 +177,8 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
return !r300screen->caps.has_tcl;
/* HWTCL-only features / limitations. */
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
return r300screen->caps.has_tcl;
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return r300screen->caps.has_tcl ? PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE : PIPE_VERTEX_INPUT_ALIGNMENT_NONE;
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:

6
src/gallium/drivers/r600/r600_pipe.c
View File

@@ -261,9 +261,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_VS_INSTANCEID:
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_START_INSTANCE:
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
@@ -291,6 +288,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
return 1;
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE;
case PIPE_CAP_NIR_ATOMICS_AS_DEREF:
case PIPE_CAP_GL_SPIRV:
return 1;

3
src/gallium/drivers/radeonsi/si_get.c
View File

@@ -280,9 +280,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
/* Allow 1/4th of the heap size. */
return sscreen->info.max_heap_size_kb / 1024 / 4;
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_PREFER_BACK_BUFFER_REUSE:
case PIPE_CAP_UMA:
case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:

10
src/gallium/drivers/svga/svga_screen.c
View File

@@ -386,14 +386,8 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
return sws->have_gl43 ? SVGA_MAX_ATOMIC_BUFFERS : 0;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return 64;
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
return sws->have_vgpu10 ? 0 : 1;
case PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY:
/* This CAP cannot be used with any other alignment-requiring CAPs */
return sws->have_vgpu10 ? 1 : 0;
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
return sws->have_vgpu10 ? 0 : 1;
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return sws->have_vgpu10 ? PIPE_VERTEX_INPUT_ALIGNMENT_ELEMENT : PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE;
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2048;
case PIPE_CAP_MAX_VIEWPORTS:

3
src/gallium/drivers/virgl/virgl_screen.c
View File

@@ -196,9 +196,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_START_INSTANCE:
return vscreen->caps.caps.v1.bset.start_instance;
case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_TEXTURE_TRANSFER_MODES:
case PIPE_CAP_NIR_IMAGES_AS_DEREF:
return 0;

4
src/gallium/drivers/zink/zink_screen.c
View File

@@ -759,8 +759,8 @@ zink_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_SWIZZLE:
return 1;
case PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY:
return !screen->info.have_EXT_legacy_vertex_attributes;
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return screen->info.have_EXT_legacy_vertex_attributes ? PIPE_VERTEX_INPUT_ALIGNMENT_NONE : PIPE_VERTEX_INPUT_ALIGNMENT_ELEMENT;
case PIPE_CAP_GL_CLAMP:
return 0;

11
src/gallium/include/pipe/p_defines.h
View File

@@ -631,6 +631,12 @@ enum pipe_reset_status
PIPE_UNKNOWN_CONTEXT_RESET,
};
enum pipe_vertex_input_alignment {
PIPE_VERTEX_INPUT_ALIGNMENT_NONE,
PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE,
PIPE_VERTEX_INPUT_ALIGNMENT_ELEMENT,
};
/**
* Conservative rasterization modes.
@@ -748,10 +754,7 @@ enum pipe_cap
PIPE_CAP_ESSL_FEATURE_LEVEL,
PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION,
PIPE_CAP_USER_VERTEX_BUFFERS,
PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY,
PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY,
PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY,
PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY,
PIPE_CAP_VERTEX_INPUT_ALIGNMENT,
PIPE_CAP_COMPUTE,
PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT,
PIPE_CAP_START_INSTANCE,