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intel/brw: Replace some fs_reg constructors with functions

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Create three helper functions for ATTR, UNIFORM and VGRF creation.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29791>
This commit is contained in:
Caio Oliveira
2024-06-18 15:25:22 -07:00
committed by Marge Bot
parent 06fbab3a74
commit d00329e821
17 changed files with 111 additions and 119 deletions
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41
src/intel/compiler/brw_fs.cpp
View File

@@ -538,34 +538,15 @@ fs_inst::can_change_types() const
!src[1].abs && !src[1].negate && src[1].file != ATTR));
}
void
fs_reg::init()
/** Generic unset register constructor. */
fs_reg::fs_reg()
{
memset((void*)this, 0, sizeof(*this));
type = BRW_TYPE_UD;
stride = 1;
}
/** Generic unset register constructor. */
fs_reg::fs_reg()
{
init();
this->file = BAD_FILE;
}
fs_reg::fs_reg(struct ::brw_reg reg) :
brw_reg(reg)
{
this->offset = 0;
this->stride = 1;
if (this->file == IMM &&
(this->type != BRW_TYPE_V &&
this->type != BRW_TYPE_UV &&
this->type != BRW_TYPE_VF)) {
this->stride = 0;
}
}
bool
brw_reg::equals(const brw_reg &r) const
{
@@ -1070,24 +1051,6 @@ fs_inst::has_sampler_residency() const
}
}
fs_reg::fs_reg(enum brw_reg_file file, unsigned nr)
{
init();
this->file = file;
this->nr = nr;
this->type = BRW_TYPE_F;
this->stride = (file == UNIFORM ? 0 : 1);
}
fs_reg::fs_reg(enum brw_reg_file file, unsigned nr, enum brw_reg_type type)
{
init();
this->file = file;
this->nr = nr;
this->type = type;
this->stride = (file == UNIFORM ? 0 : 1);
}
/* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
* This brings in those uniform definitions
*/

2
src/intel/compiler/brw_fs.h
View File

@@ -608,7 +608,7 @@ namespace brw {
inline fs_reg
dynamic_msaa_flags(const struct brw_wm_prog_data *wm_prog_data)
{
return fs_reg(UNIFORM, wm_prog_data->msaa_flags_param, BRW_TYPE_UD);
return brw_uniform_reg(wm_prog_data->msaa_flags_param, BRW_TYPE_UD);
}
void

8
src/intel/compiler/brw_fs_builder.h
View File

@@ -191,10 +191,10 @@ namespace brw {
assert(dispatch_width() <= 32);
if (n > 0)
return fs_reg(VGRF, shader->alloc.allocate(
DIV_ROUND_UP(n * brw_type_size_bytes(type) * dispatch_width(),
unit * REG_SIZE) * unit),
type);
return brw_vgrf(shader->alloc.allocate(
DIV_ROUND_UP(n * brw_type_size_bytes(type) * dispatch_width(),
unit * REG_SIZE) * unit),
type);
else
return retype(null_reg_ud(), type);
}

4
src/intel/compiler/brw_fs_combine_constants.cpp
View File

@@ -1172,7 +1172,7 @@ allocate_slots(struct register_allocation *regs, unsigned num_regs,
regs[i].avail &= ~(mask << j);
fs_reg reg(VGRF, regs[i].nr);
fs_reg reg = brw_vgrf(regs[i].nr, BRW_TYPE_F);
reg.offset = j * 2;
return reg;
@@ -1569,7 +1569,7 @@ brw_fs_opt_combine_constants(fs_visitor &s)
const uint32_t width = 1;
const fs_builder ibld = fs_builder(&s, width).at(insert_block, n).exec_all();
fs_reg reg(VGRF, imm->nr);
fs_reg reg = brw_vgrf(imm->nr, BRW_TYPE_F);
reg.offset = imm->subreg_offset;
reg.stride = 0;

2
src/intel/compiler/brw_fs_cse.cpp
View File

@@ -383,7 +383,7 @@ remap_sources(fs_visitor &s, const brw::def_analysis &defs,
if (def_block->end_ip_delta)
s.cfg->adjust_block_ips();
fs_reg neg(VGRF, new_nr, BRW_TYPE_F);
fs_reg neg = brw_vgrf(new_nr, BRW_TYPE_F);
fs_reg tmp = dbld.MOV(negate(neg));
inst->src[i].nr = tmp.nr;
remap_table[old_nr] = tmp.nr;

9
src/intel/compiler/brw_fs_lower.cpp
View File

@@ -553,8 +553,9 @@ brw_fs_lower_sends_overlapping_payload(fs_visitor &s)
const unsigned arg = inst->mlen < inst->ex_mlen ? 2 : 3;
const unsigned len = MIN2(inst->mlen, inst->ex_mlen);
fs_reg tmp = fs_reg(VGRF, s.alloc.allocate(len),
BRW_TYPE_UD);
fs_reg tmp = brw_vgrf(s.alloc.allocate(len),
BRW_TYPE_UD);
/* Sadly, we've lost all notion of channels and bit sizes at this
* point. Just WE_all it.
*/
@@ -593,8 +594,8 @@ brw_fs_lower_3src_null_dest(fs_visitor &s)
foreach_block_and_inst_safe (block, fs_inst, inst, s.cfg) {
if (inst->is_3src(s.compiler) && inst->dst.is_null()) {
inst->dst = fs_reg(VGRF, s.alloc.allocate(s.dispatch_width / 8),
inst->dst.type);
inst->dst = brw_vgrf(s.alloc.allocate(s.dispatch_width / 8),
inst->dst.type);
progress = true;
}
}

16
src/intel/compiler/brw_fs_lower_integer_multiplication.cpp
View File

@@ -222,12 +222,12 @@ brw_fs_lower_mul_dword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block)
inst->src[1], inst->size_read(1)) ||
inst->dst.stride >= 4) {
needs_mov = true;
low = fs_reg(VGRF, s.alloc.allocate(regs_written(inst)),
inst->dst.type);
low = brw_vgrf(s.alloc.allocate(regs_written(inst)),
inst->dst.type);
}
/* Get a new VGRF but keep the same stride as inst->dst */
fs_reg high(VGRF, s.alloc.allocate(regs_written(inst)), inst->dst.type);
fs_reg high = brw_vgrf(s.alloc.allocate(regs_written(inst)), inst->dst.type);
high.stride = inst->dst.stride;
high.offset = inst->dst.offset % REG_SIZE;
@@ -319,17 +319,17 @@ brw_fs_lower_mul_qword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block)
unsigned int q_regs = regs_written(inst);
unsigned int d_regs = (q_regs + 1) / 2;
fs_reg bd(VGRF, s.alloc.allocate(q_regs), BRW_TYPE_UQ);
fs_reg ad(VGRF, s.alloc.allocate(d_regs), BRW_TYPE_UD);
fs_reg bc(VGRF, s.alloc.allocate(d_regs), BRW_TYPE_UD);
fs_reg bd = brw_vgrf(s.alloc.allocate(q_regs), BRW_TYPE_UQ);
fs_reg ad = brw_vgrf(s.alloc.allocate(d_regs), BRW_TYPE_UD);
fs_reg bc = brw_vgrf(s.alloc.allocate(d_regs), BRW_TYPE_UD);
/* Here we need the full 64 bit result for 32b * 32b. */
if (devinfo->has_integer_dword_mul) {
ibld.MUL(bd, subscript(inst->src[0], BRW_TYPE_UD, 0),
subscript(inst->src[1], BRW_TYPE_UD, 0));
} else {
fs_reg bd_high(VGRF, s.alloc.allocate(d_regs), BRW_TYPE_UD);
fs_reg bd_low(VGRF, s.alloc.allocate(d_regs), BRW_TYPE_UD);
fs_reg bd_high = brw_vgrf(s.alloc.allocate(d_regs), BRW_TYPE_UD);
fs_reg bd_low = brw_vgrf(s.alloc.allocate(d_regs), BRW_TYPE_UD);
const unsigned acc_width = reg_unit(devinfo) * 8;
fs_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), BRW_TYPE_UD),
inst->group % acc_width);

2
src/intel/compiler/brw_fs_lower_regioning.cpp
View File

@@ -549,7 +549,7 @@ namespace {
inst->exec_size * stride *
brw_type_size_bytes(inst->src[i].type),
reg_unit(devinfo) * REG_SIZE) * reg_unit(devinfo);
fs_reg tmp(VGRF, v->alloc.allocate(size), inst->src[i].type);
fs_reg tmp = brw_vgrf(v->alloc.allocate(size), inst->src[i].type);
ibld.UNDEF(tmp);
tmp = byte_offset(horiz_stride(tmp, stride),
required_src_byte_offset(devinfo, inst, i));

38
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -2596,7 +2596,7 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst,
nir_src_as_uint(vertex_src) * push_reg_count;
fs_reg comps[num_components];
const fs_reg attr = fs_reg(ATTR, 0, dst.type);
const fs_reg attr = brw_attr_reg(0, dst.type);
for (unsigned i = 0; i < num_components; i++) {
comps[i] = offset(attr, bld, imm_offset + i + first_component);
}
@@ -2776,7 +2776,7 @@ fs_nir_emit_vs_intrinsic(nir_to_brw_state &ntb,
case nir_intrinsic_load_input: {
assert(instr->def.bit_size == 32);
const fs_reg src = offset(fs_reg(ATTR, 0, dest.type), bld,
const fs_reg src = offset(brw_attr_reg(0, dest.type), bld,
nir_intrinsic_base(instr) * 4 +
nir_intrinsic_component(instr) +
nir_src_as_uint(instr->src[0]));
@@ -2932,7 +2932,7 @@ emit_barrier(nir_to_brw_state &ntb)
/* We are getting the barrier ID from the compute shader header */
assert(gl_shader_stage_uses_workgroup(s.stage));
fs_reg payload = fs_reg(VGRF, s.alloc.allocate(1), BRW_TYPE_UD);
fs_reg payload = brw_vgrf(s.alloc.allocate(1), BRW_TYPE_UD);
/* Clear the message payload */
bld.exec_all().group(8, 0).MOV(payload, brw_imm_ud(0u));
@@ -3285,7 +3285,7 @@ fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb,
*/
const unsigned max_push_slots = 32;
if (imm_offset < max_push_slots) {
const fs_reg src = horiz_offset(fs_reg(ATTR, 0, dest.type),
const fs_reg src = horiz_offset(brw_attr_reg(0, dest.type),
4 * imm_offset + first_component);
fs_reg comps[instr->num_components];
for (unsigned i = 0; i < instr->num_components; i++) {
@@ -4816,8 +4816,8 @@ try_rebuild_source(nir_to_brw_state &ntb, const brw::fs_builder &bld,
case nir_intrinsic_load_uniform: {
unsigned base_offset = nir_intrinsic_base(intrin);
unsigned load_offset = nir_src_as_uint(intrin->src[0]);
fs_reg src(UNIFORM, base_offset / 4,
brw_type_with_size(BRW_TYPE_D, intrin->def.bit_size));
fs_reg src = brw_uniform_reg(base_offset / 4,
brw_type_with_size(BRW_TYPE_D, intrin->def.bit_size));
src.offset = load_offset + base_offset % 4;
return src;
}
@@ -4972,8 +4972,8 @@ try_rebuild_source(nir_to_brw_state &ntb, const brw::fs_builder &bld,
unsigned base_offset = nir_intrinsic_base(intrin);
unsigned load_offset = nir_src_as_uint(intrin->src[0]);
fs_reg src(UNIFORM, base_offset / 4,
brw_type_with_size(BRW_TYPE_D, intrin->def.bit_size));
fs_reg src = brw_uniform_reg(base_offset / 4,
brw_type_with_size(BRW_TYPE_D, intrin->def.bit_size));
src.offset = load_offset + base_offset % 4;
ubld8.MOV(src, &ntb.resource_insts[def->index]);
break;
@@ -5288,7 +5288,7 @@ get_timestamp(const fs_builder &bld)
fs_reg ts = fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_TIMESTAMP, 0), BRW_TYPE_UD));
fs_reg dst = fs_reg(VGRF, s.alloc.allocate(1), BRW_TYPE_UD);
fs_reg dst = brw_vgrf(s.alloc.allocate(1), BRW_TYPE_UD);
/* We want to read the 3 fields we care about even if it's not enabled in
* the dispatch.
@@ -5349,8 +5349,8 @@ emit_urb_direct_vec4_write(const fs_builder &bld,
fs_reg srcs[URB_LOGICAL_NUM_SRCS];
srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle;
srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(mask << 16);
srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, bld.shader->alloc.allocate(length),
BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_DATA] = brw_vgrf(bld.shader->alloc.allocate(length),
BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length);
bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0);
@@ -5419,7 +5419,7 @@ emit_urb_direct_vec4_write_xe2(const fs_builder &bld,
srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle;
srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(mask << 16);
int nr = bld.shader->alloc.allocate(comps * runit);
srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, nr, BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_DATA] = brw_vgrf(nr, BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(comps);
hbld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, comps, 0);
@@ -5481,8 +5481,8 @@ emit_urb_indirect_vec4_write(const fs_builder &bld,
srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle;
srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = off;
srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(mask << 16);
srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, bld.shader->alloc.allocate(length),
BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_DATA] = brw_vgrf(bld.shader->alloc.allocate(length),
BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length);
bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0);
@@ -5553,7 +5553,7 @@ emit_urb_indirect_writes_xe2(const fs_builder &bld, nir_intrinsic_instr *instr,
srcs[URB_LOGICAL_SRC_HANDLE] = addr;
srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(mask << 16);
int nr = bld.shader->alloc.allocate(comps * runit);
srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, nr, BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_DATA] = brw_vgrf(nr, BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(comps);
wbld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, comps, 0);
@@ -5612,8 +5612,8 @@ emit_urb_indirect_writes(const fs_builder &bld, nir_intrinsic_instr *instr,
srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle;
srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = final_offset;
srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = mask;
srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, bld.shader->alloc.allocate(length),
BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_DATA] = brw_vgrf(bld.shader->alloc.allocate(length),
BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length);
bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0);
@@ -6466,7 +6466,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
unsigned base_offset = nir_intrinsic_base(instr);
assert(base_offset % 4 == 0 || base_offset % brw_type_size_bytes(dest.type) == 0);
fs_reg src(UNIFORM, base_offset / 4, dest.type);
fs_reg src = brw_uniform_reg(base_offset / 4, dest.type);
if (nir_src_is_const(instr->src[0])) {
unsigned load_offset = nir_src_as_uint(instr->src[0]);
@@ -6635,7 +6635,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
offset_256b >= range->start &&
end_256b <= range->start + range->length) {
push_reg = fs_reg(UNIFORM, UBO_START + i, dest.type);
push_reg = brw_uniform_reg(UBO_START + i, dest.type);
push_reg.offset = load_offset - 32 * range->start;
break;
}

4
src/intel/compiler/brw_fs_opt.cpp
View File

@@ -324,8 +324,8 @@ brw_fs_opt_split_sends(fs_visitor &s)
assert(lp2->size_written % REG_SIZE == 0);
assert((lp1->size_written + lp2->size_written) / REG_SIZE == send->mlen);
lp1->dst = fs_reg(VGRF, s.alloc.allocate(lp1->size_written / REG_SIZE), lp1->dst.type);
lp2->dst = fs_reg(VGRF, s.alloc.allocate(lp2->size_written / REG_SIZE), lp2->dst.type);
lp1->dst = brw_vgrf(s.alloc.allocate(lp1->size_written / REG_SIZE), lp1->dst.type);
lp2->dst = brw_vgrf(s.alloc.allocate(lp2->size_written / REG_SIZE), lp2->dst.type);
send->resize_sources(4);
send->src[2] = lp1->dst;

2
src/intel/compiler/brw_fs_opt_virtual_grfs.cpp
View File

@@ -150,7 +150,7 @@ brw_fs_opt_split_virtual_grfs(fs_visitor &s)
reg = vgrf_to_reg[inst->dst.nr] + reg_offset + size_written / REG_SIZE;
fs_inst *undef =
ibld.UNDEF(
byte_offset(fs_reg(VGRF, new_virtual_grf[reg], inst->dst.type),
byte_offset(brw_vgrf(new_virtual_grf[reg], inst->dst.type),
new_reg_offset[reg] * REG_SIZE));
undef->size_written =
MIN2(inst->size_written - size_written, undef->size_written);

2
src/intel/compiler/brw_fs_reg_allocate.cpp
View File

@@ -933,7 +933,7 @@ fs_reg_alloc::alloc_spill_reg(unsigned size, int ip)
}
spill_vgrf_ip[spill_node_count++] = ip;
return fs_reg(VGRF, vgrf);
return brw_vgrf(vgrf, BRW_TYPE_F);
}
void

2
src/intel/compiler/brw_fs_thread_payload.cpp
View File

@@ -399,7 +399,7 @@ cs_thread_payload::load_subgroup_id(const fs_builder &bld,
assert(gl_shader_stage_is_compute(bld.shader->stage));
int index = brw_get_subgroup_id_param_index(devinfo,
bld.shader->prog_data);
bld.MOV(dest, fs_reg(UNIFORM, index, BRW_TYPE_UD));
bld.MOV(dest, brw_uniform_reg(index, BRW_TYPE_UD));
}
}

39
src/intel/compiler/brw_fs_visitor.cpp
View File

@@ -72,11 +72,11 @@ fs_visitor::interp_reg(const fs_builder &bld, unsigned location,
* component() to select the specified parameter.
*/
const fs_reg tmp = bld.vgrf(BRW_TYPE_UD);
bld.MOV(tmp, offset(fs_reg(ATTR, regnr, BRW_TYPE_UD),
bld.MOV(tmp, offset(brw_attr_reg(regnr, BRW_TYPE_UD),
dispatch_width, comp));
return retype(tmp, BRW_TYPE_F);
} else {
return component(fs_reg(ATTR, regnr, BRW_TYPE_F), comp);
return component(brw_attr_reg(regnr, BRW_TYPE_F), comp);
}
}
@@ -107,11 +107,11 @@ fs_visitor::per_primitive_reg(const fs_builder &bld, int location, unsigned comp
* component() to select the specified parameter.
*/
const fs_reg tmp = bld.vgrf(BRW_TYPE_UD);
bld.MOV(tmp, offset(fs_reg(ATTR, regnr, BRW_TYPE_UD),
bld.MOV(tmp, offset(brw_attr_reg(regnr, BRW_TYPE_UD),
dispatch_width, comp % 4));
return retype(tmp, BRW_TYPE_F);
} else {
return component(fs_reg(ATTR, regnr, BRW_TYPE_F), comp % 4);
return component(brw_attr_reg(regnr, BRW_TYPE_F), comp % 4);
}
}
@@ -760,8 +760,8 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
break;
}
fs_reg zero(VGRF, alloc.allocate(dispatch_width / 8),
BRW_TYPE_UD);
fs_reg zero = brw_vgrf(alloc.allocate(dispatch_width / 8),
BRW_TYPE_UD);
bld.MOV(zero, brw_imm_ud(0u));
if (vue_map->slots_valid & VARYING_BIT_PRIMITIVE_SHADING_RATE &&
@@ -769,8 +769,8 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
sources[length++] = this->outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE];
} else if (devinfo->has_coarse_pixel_primitive_and_cb) {
uint32_t one_fp16 = 0x3C00;
fs_reg one_by_one_fp16(VGRF, alloc.allocate(dispatch_width / 8),
BRW_TYPE_UD);
fs_reg one_by_one_fp16 = brw_vgrf(alloc.allocate(dispatch_width / 8),
BRW_TYPE_UD);
bld.MOV(one_by_one_fp16, brw_imm_ud((one_fp16 << 16) | one_fp16));
sources[length++] = one_by_one_fp16;
} else {
@@ -843,9 +843,8 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle;
srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = per_slot_offsets;
srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF,
alloc.allocate((dispatch_width / 8) * length),
BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_DATA] = brw_vgrf(alloc.allocate((dispatch_width / 8) * length),
BRW_TYPE_F);
srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length);
abld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, length, 0);
@@ -884,10 +883,10 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
if (stage == MESA_SHADER_GEOMETRY)
return;
fs_reg uniform_urb_handle = fs_reg(VGRF, alloc.allocate(dispatch_width / 8),
BRW_TYPE_UD);
fs_reg payload = fs_reg(VGRF, alloc.allocate(dispatch_width / 8),
BRW_TYPE_UD);
fs_reg uniform_urb_handle = brw_vgrf(alloc.allocate(dispatch_width / 8),
BRW_TYPE_UD);
fs_reg payload = brw_vgrf(alloc.allocate(dispatch_width / 8),
BRW_TYPE_UD);
bld.exec_all().MOV(uniform_urb_handle, urb_handle);
@@ -911,9 +910,9 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
*/
if (intel_needs_workaround(devinfo, 1805992985) && stage == MESA_SHADER_TESS_EVAL) {
assert(dispatch_width == 8);
fs_reg uniform_urb_handle = fs_reg(VGRF, alloc.allocate(1), BRW_TYPE_UD);
fs_reg uniform_mask = fs_reg(VGRF, alloc.allocate(1), BRW_TYPE_UD);
fs_reg payload = fs_reg(VGRF, alloc.allocate(4), BRW_TYPE_UD);
fs_reg uniform_urb_handle = brw_vgrf(alloc.allocate(1), BRW_TYPE_UD);
fs_reg uniform_mask = brw_vgrf(alloc.allocate(1), BRW_TYPE_UD);
fs_reg payload = brw_vgrf(alloc.allocate(4), BRW_TYPE_UD);
/* Workaround requires all 8 channels (lanes) to be valid. This is
* understood to mean they all need to be alive. First trick is to find
@@ -984,8 +983,8 @@ fs_visitor::emit_cs_terminate()
* make sure it uses the appropriate register range.
*/
struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_TYPE_UD);
fs_reg payload = fs_reg(VGRF, alloc.allocate(reg_unit(devinfo)),
BRW_TYPE_UD);
fs_reg payload = brw_vgrf(alloc.allocate(reg_unit(devinfo)),
BRW_TYPE_UD);
ubld.group(8 * reg_unit(devinfo), 0).MOV(payload, g0);
/* Set the descriptor to "Dereference Resource" and "Root Thread" */

6
src/intel/compiler/brw_ir_fs.h
View File

@@ -30,12 +30,8 @@
class fs_reg : public brw_reg {
public:
void init();
fs_reg();
fs_reg(struct ::brw_reg reg);
fs_reg(enum brw_reg_file file, unsigned nr);
fs_reg(enum brw_reg_file file, unsigned nr, enum brw_reg_type type);
fs_reg(struct ::brw_reg reg) : brw_reg(reg) {}
};
static inline fs_reg

20
src/intel/compiler/brw_lower_logical_sends.cpp
View File

@@ -47,8 +47,8 @@ lower_urb_read_logical_send(const fs_builder &bld, fs_inst *inst)
if (per_slot_present)
payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS];
fs_reg payload = fs_reg(VGRF, bld.shader->alloc.allocate(header_size),
BRW_TYPE_F);
fs_reg payload = brw_vgrf(bld.shader->alloc.allocate(header_size),
BRW_TYPE_F);
bld.LOAD_PAYLOAD(payload, payload_sources, header_size, header_size);
inst->opcode = SHADER_OPCODE_SEND;
@@ -148,8 +148,8 @@ lower_urb_write_logical_send(const fs_builder &bld, fs_inst *inst)
inst->components_read(URB_LOGICAL_SRC_DATA);
fs_reg *payload_sources = new fs_reg[length];
fs_reg payload = fs_reg(VGRF, bld.shader->alloc.allocate(length),
BRW_TYPE_F);
fs_reg payload = brw_vgrf(bld.shader->alloc.allocate(length),
BRW_TYPE_F);
unsigned header_size = 0;
payload_sources[header_size++] = inst->src[URB_LOGICAL_SRC_HANDLE];
@@ -376,7 +376,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
if (fs_payload.aa_dest_stencil_reg[0]) {
assert(inst->group < 16);
sources[length] = fs_reg(VGRF, bld.shader->alloc.allocate(1));
sources[length] = brw_vgrf(bld.shader->alloc.allocate(1), BRW_TYPE_F);
bld.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
.MOV(sources[length],
fs_reg(brw_vec8_grf(fs_payload.aa_dest_stencil_reg[0], 0)));
@@ -395,8 +395,8 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
}
if (sample_mask.file != BAD_FILE) {
const fs_reg tmp(VGRF, bld.shader->alloc.allocate(reg_unit(devinfo)),
BRW_TYPE_UD);
const fs_reg tmp = brw_vgrf(bld.shader->alloc.allocate(reg_unit(devinfo)),
BRW_TYPE_UD);
/* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
* relevant. Since it's unsigned single words one vgrf is always
@@ -455,7 +455,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
}
/* Send from the GRF */
fs_reg payload = fs_reg(VGRF, -1, BRW_TYPE_F);
fs_reg payload = brw_vgrf(-1, BRW_TYPE_F);
fs_inst *load = bld.LOAD_PAYLOAD(payload, sources, length, payload_header_size);
payload.nr = bld.shader->alloc.allocate(regs_written(load));
load->dst = payload;
@@ -1088,8 +1088,8 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
}
const fs_reg src_payload =
fs_reg(VGRF, bld.shader->alloc.allocate(length * reg_width),
BRW_TYPE_F);
brw_vgrf(bld.shader->alloc.allocate(length * reg_width),
BRW_TYPE_F);
/* In case of 16-bit payload each component takes one full register in
* both SIMD8H and SIMD16H modes. In both cases one reg can hold 16
* elements. In SIMD8H case hardware simply expects the components to be

33
src/intel/compiler/brw_reg.h
View File

@@ -975,6 +975,39 @@ brw_mask_stack_depth_reg(unsigned subnr)
BRW_ARF_MASK_STACK_DEPTH, subnr);
}
static inline struct brw_reg
brw_vgrf(unsigned nr, enum brw_reg_type type)
{
struct brw_reg reg = {};
reg.file = VGRF;
reg.nr = nr;
reg.type = type;
reg.stride = 1;
return reg;
}
static inline struct brw_reg
brw_attr_reg(unsigned nr, enum brw_reg_type type)
{
struct brw_reg reg = {};
reg.file = ATTR;
reg.nr = nr;
reg.type = type;
reg.stride = 1;
return reg;
}
static inline struct brw_reg
brw_uniform_reg(unsigned nr, enum brw_reg_type type)
{
struct brw_reg reg = {};
reg.file = UNIFORM;
reg.nr = nr;
reg.type = type;
reg.stride = 0;
return reg;
}
/* This is almost always called with a numeric constant argument, so
* make things easy to evaluate at compile time:
*/