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Convert i915tex to the new interface and make it compile.

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This commit is contained in:
Eric Anholt
2007-05-17 15:28:01 -07:00
parent 7b971a5008
commit cfc21190af
30 changed files with 320 additions and 803 deletions
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6
src/mesa/drivers/dri/common/dri_bufmgr.c
View File

@@ -85,6 +85,12 @@ dri_fence_validated(dri_bufmgr *bufmgr, const char *name, GLboolean flushed)
return bufmgr->fence_validated(bufmgr, name, flushed);
}
void
dri_fence_wait(dri_fence *fence)
{
fence->bufmgr->fence_wait(fence);
}
void
dri_fence_reference(dri_fence *fence)
{

12
src/mesa/drivers/dri/common/dri_bufmgr.h
View File

@@ -164,17 +164,6 @@ struct _dri_bufmgr {
*/
};
/*
extern void driBOData(struct _DriBufferObject *r_buf,
unsigned size, const void *data, unsigned flags);
extern void driBOSubData(struct _DriBufferObject *buf,
unsigned long offset, unsigned long size,
const void *data);
extern void driBOGetSubData(struct _DriBufferObject *buf,
unsigned long offset, unsigned long size,
void *data);
*/
dri_bo *dri_bo_alloc(dri_bufmgr *bufmgr, const char *name, unsigned long size,
unsigned int alignment, unsigned int flags,
unsigned int hint);
@@ -189,6 +178,7 @@ int dri_bo_unmap(dri_bo *buf);
int dri_bo_validate(dri_bo *buf, unsigned int flags);
dri_fence *dri_fence_validated(dri_bufmgr *bufmgr, const char *name,
GLboolean flushed);
void dri_fence_wait(dri_fence *fence);
void dri_fence_reference(dri_fence *fence);
void dri_fence_unreference(dri_fence *fence);

3
src/mesa/drivers/dri/i915tex/Makefile
View File

@@ -50,8 +50,7 @@ DRIVER_SOURCES = \
intel_state.c \
intel_tris.c \
intel_fbo.c \
intel_depthstencil.c \
intel_batchpool.c
intel_depthstencil.c
C_SOURCES = \
$(COMMON_SOURCES) \

6
src/mesa/drivers/dri/i915tex/i830_context.h
View File

@@ -114,10 +114,10 @@ struct i830_hw_state
struct intel_region *depth_region;
/* Regions aren't actually that appropriate here as the memory may
* be from a PBO or FBO. Just use the buffer id. Will have to do
* this for draw and depth for FBO's...
* be from a PBO or FBO. Will have to do this for draw and depth for
* FBO's...
*/
struct _DriBufferObject *tex_buffer[I830_TEX_UNITS];
dri_bo *tex_buffer[I830_TEX_UNITS];
GLuint tex_offset[I830_TEX_UNITS];
GLuint emitted; /* I810_UPLOAD_* */

2
src/mesa/drivers/dri/i915tex/i830_metaops.c
View File

@@ -238,7 +238,7 @@ set_texture_blend_replace(struct intel_context *intel)
*/
static GLboolean
set_tex_rect_source(struct intel_context *intel,
struct _DriBufferObject *buffer,
dri_bo *buffer,
GLuint offset,
GLuint pitch, GLuint height, GLenum format, GLenum type)
{

7
src/mesa/drivers/dri/i915tex/i830_texstate.c
View File

@@ -124,7 +124,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
/*We need to refcount these. */
if (i830->state.tex_buffer[unit] != NULL) {
driBOUnReference(i830->state.tex_buffer[unit]);
dri_bo_unreference(i830->state.tex_buffer[unit]);
i830->state.tex_buffer[unit] = NULL;
}
@@ -136,7 +136,8 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
*/
firstImage = tObj->Image[0][intelObj->firstLevel];
i830->state.tex_buffer[unit] = driBOReference(intelObj->mt->region->buffer);
dri_bo_reference(intelObj->mt->region->buffer);
i830->state.tex_buffer[unit] = intelObj->mt->region->buffer;
i830->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt, 0,
intelObj->
firstLevel);
@@ -303,7 +304,7 @@ i830UpdateTextureState(struct intel_context *intel)
I830_ACTIVESTATE(i830, I830_UPLOAD_TEX(i), GL_FALSE);
if (i830->state.tex_buffer[i] != NULL) {
driBOUnReference(i830->state.tex_buffer[i]);
dri_bo_unreference(i830->state.tex_buffer[i]);
i830->state.tex_buffer[i] = NULL;
}
break;

3
src/mesa/drivers/dri/i915tex/i830_vtbl.c
View File

@@ -451,7 +451,6 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
state->draw_region->draw_offset);
if (state->depth_region) {
@@ -459,7 +458,6 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
state->depth_region->draw_offset);
}
@@ -487,7 +485,6 @@ i830_emit_state(struct intel_context *intel)
if (state->tex_buffer[i]) {
OUT_RELOC(state->tex_buffer[i],
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_BO_MASK_MEM | DRM_BO_FLAG_READ,
state->tex_offset[i] | TM0S0_USE_FENCE);
}
else {

6
src/mesa/drivers/dri/i915tex/i915_context.h
View File

@@ -219,10 +219,10 @@ struct i915_hw_state
/* struct intel_region *tex_region[I915_TEX_UNITS]; */
/* Regions aren't actually that appropriate here as the memory may
* be from a PBO or FBO. Just use the buffer id. Will have to do
* this for draw and depth for FBO's...
* be from a PBO or FBO. Will have to do this for draw and depth for
* FBO's...
*/
struct _DriBufferObject *tex_buffer[I915_TEX_UNITS];
dri_bo *tex_buffer[I915_TEX_UNITS];
GLuint tex_offset[I915_TEX_UNITS];

2
src/mesa/drivers/dri/i915tex/i915_metaops.c
View File

@@ -326,7 +326,7 @@ meta_texture_blend_replace(struct intel_context *intel)
*/
static GLboolean
meta_tex_rect_source(struct intel_context *intel,
struct _DriBufferObject *buffer,
dri_bo *buffer,
GLuint offset,
GLuint pitch, GLuint height, GLenum format, GLenum type)
{

8
src/mesa/drivers/dri/i915tex/i915_texstate.c
View File

@@ -129,7 +129,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
/*We need to refcount these. */
if (i915->state.tex_buffer[unit] != NULL) {
driBOUnReference(i915->state.tex_buffer[unit]);
dri_bo_unreference(i915->state.tex_buffer[unit]);
i915->state.tex_buffer[unit] = NULL;
}
@@ -141,7 +141,9 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
*/
firstImage = tObj->Image[0][intelObj->firstLevel];
i915->state.tex_buffer[unit] = driBOReference(intelObj->mt->region->buffer);
dri_bo_reference(intelObj->mt->region->buffer);
i915->state.tex_buffer[unit] = intelObj->mt->region->buffer;
i915->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt, 0,
intelObj->
firstLevel);
@@ -322,7 +324,7 @@ i915UpdateTextureState(struct intel_context *intel)
I915_ACTIVESTATE(i915, I915_UPLOAD_TEX(i), GL_FALSE);
if (i915->state.tex_buffer[i] != NULL) {
driBOUnReference(i915->state.tex_buffer[i]);
dri_bo_unreference(i915->state.tex_buffer[i]);
i915->state.tex_buffer[i] = NULL;
}

3
src/mesa/drivers/dri/i915tex/i915_vtbl.c
View File

@@ -326,7 +326,6 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
state->draw_region->draw_offset);
if (state->depth_region) {
@@ -334,7 +333,6 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
state->depth_region->draw_offset);
}
@@ -378,7 +376,6 @@ i915_emit_state(struct intel_context *intel)
if (state->tex_buffer[i]) {
OUT_RELOC(state->tex_buffer[i],
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_BO_MASK_MEM | DRM_BO_FLAG_READ,
state->tex_offset[i]);
}
else {

174
src/mesa/drivers/dri/i915tex/intel_batchbuffer.c
View File

@@ -77,49 +77,6 @@ intel_dump_batchbuffer(GLuint offset, GLuint * ptr, GLuint count)
fprintf(stderr, "END BATCH\n\n\n");
}
void
intel_batchbuffer_reset(struct intel_batchbuffer *batch)
{
int i;
/*
* Get a new, free batchbuffer.
*/
batch->size = batch->intel->intelScreen->maxBatchSize;
driBOData(batch->buffer, batch->size, NULL, 0);
driBOResetList(&batch->list);
/*
* Unreference buffers previously on the relocation list.
*/
for (i = 0; i < batch->nr_relocs; i++) {
struct buffer_reloc *r = &batch->reloc[i];
driBOUnReference(r->buf);
}
batch->list_count = 0;
batch->nr_relocs = 0;
batch->flags = 0;
/*
* We don't refcount the batchbuffer itself since we can't destroy it
* while it's on the list.
*/
driBOAddListItem(&batch->list, batch->buffer,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_EXE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_EXE);
batch->map = driBOMap(batch->buffer, DRM_BO_FLAG_WRITE, 0);
batch->ptr = batch->map;
}
/*======================================================================
* Public functions
*/
@@ -129,12 +86,16 @@ intel_batchbuffer_alloc(struct intel_context *intel)
struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
batch->intel = intel;
batch->buf = dri_bo_alloc(intel->intelScreen->bufmgr, "batchbuffer",
intel->intelScreen->maxBatchSize, 4096,
DRM_BO_FLAG_MEM_TT |
DRM_BO_FLAG_EXE, 0);
dri_bo_map(batch->buf, GL_TRUE);
batch->map = batch->buf->virtual;
batch->size = intel->intelScreen->maxBatchSize;
batch->ptr = batch->map;
driGenBuffers(intel->intelScreen->batchPool, "batchbuffer", 1,
&batch->buffer, 4096,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_EXE, 0);
batch->last_fence = NULL;
driBOCreateList(20, &batch->list);
intel_batchbuffer_reset(batch);
return batch;
}
@@ -143,17 +104,16 @@ void
intel_batchbuffer_free(struct intel_batchbuffer *batch)
{
if (batch->last_fence) {
driFenceFinish(batch->last_fence,
DRM_FENCE_TYPE_EXE | DRM_I915_FENCE_TYPE_RW, GL_FALSE);
driFenceUnReference(batch->last_fence);
dri_fence_wait(batch->last_fence);
dri_fence_unreference(batch->last_fence);
batch->last_fence = NULL;
}
if (batch->map) {
driBOUnmap(batch->buffer);
dri_bo_unmap(batch->buf);
batch->map = NULL;
}
driBOUnReference(batch->buffer);
batch->buffer = NULL;
dri_bo_unreference(batch->buf);
batch->buf = NULL;
free(batch);
}
@@ -167,30 +127,35 @@ do_flush_locked(struct intel_batchbuffer *batch,
GLuint *ptr;
GLuint i;
struct intel_context *intel = batch->intel;
unsigned fenceFlags;
struct _DriFenceObject *fo;
driBOValidateList(batch->intel->driFd, &batch->list);
/* Apply the relocations. This nasty map indicates to me that the
* whole task should be done internally by the memory manager, and
* that dma buffers probably need to be pinned within agp space.
*/
ptr = (GLuint *) driBOMap(batch->buffer, DRM_BO_FLAG_WRITE,
DRM_BO_HINT_ALLOW_UNFENCED_MAP);
dri_fence *fo;
GLboolean performed_rendering = GL_FALSE;
assert(batch->buf->virtual != NULL);
ptr = batch->buf->virtual;
for (i = 0; i < batch->nr_relocs; i++) {
struct buffer_reloc *r = &batch->reloc[i];
ptr[r->offset / 4] = driBOOffset(r->buf) + r->delta;
if (r->validate_flags & DRM_BO_FLAG_WRITE)
performed_rendering = GL_TRUE;
dri_bo_validate(r->buf, r->validate_flags);
ptr[r->offset / 4] = r->buf->offset + r->delta;
dri_bo_unreference(r->buf);
}
if (INTEL_DEBUG & DEBUG_BATCH)
intel_dump_batchbuffer(0, ptr, used);
driBOUnmap(batch->buffer);
dri_bo_unmap(batch->buf);
batch->map = NULL;
batch->ptr = NULL;
dri_bo_validate(batch->buf, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_EXE);
batch->list_count = 0;
batch->nr_relocs = 0;
batch->flags = 0;
/* Throw away non-effective packets. Won't work once we have
* hardware contexts which would preserve statechanges beyond a
@@ -199,45 +164,32 @@ do_flush_locked(struct intel_batchbuffer *batch,
if (!(intel->numClipRects == 0 && !ignore_cliprects)) {
intel_batch_ioctl(batch->intel,
driBOOffset(batch->buffer),
batch->buf->offset,
used, ignore_cliprects, allow_unlock);
}
/*
* Kernel fencing. The flags tells the kernel that we've
* programmed an MI_FLUSH.
/* Associate a fence with the validated buffers, and note that we included
* a flush at the end.
*/
fo = dri_fence_validated(intel->intelScreen->bufmgr,
"Batch fence", GL_TRUE);
fenceFlags = DRM_I915_FENCE_FLAG_FLUSHED;
fo = driFenceBuffers(batch->intel->driFd,
"Batch fence", fenceFlags);
/*
* User space fencing.
*/
driBOFence(batch->buffer, fo);
if (driFenceType(fo) == DRM_FENCE_TYPE_EXE) {
/*
* Oops. We only validated a batch buffer. This means we
* didn't do any proper rendering. Discard this fence object.
*/
driFenceUnReference(fo);
} else {
driFenceUnReference(batch->last_fence);
if (performed_rendering) {
dri_fence_unreference(batch->last_fence);
batch->last_fence = fo;
for (i = 0; i < batch->nr_relocs; i++) {
struct buffer_reloc *r = &batch->reloc[i];
driBOFence(r->buf, fo);
}
} else {
/* If we didn't validate any buffers for writing by the card, we don't
* need to track the fence for glFinish().
*/
dri_fence_unreference(fo);
}
if (intel->numClipRects == 0 && !ignore_cliprects) {
if (allow_unlock) {
/* If we are not doing any actual user-visible rendering,
* do a sched_yield to keep the app from pegging the cpu while
* achieving nothing.
*/
UNLOCK_HARDWARE(intel);
sched_yield();
LOCK_HARDWARE(intel);
@@ -247,7 +199,7 @@ do_flush_locked(struct intel_batchbuffer *batch,
}
struct _DriFenceObject *
void
intel_batchbuffer_flush(struct intel_batchbuffer *batch)
{
struct intel_context *intel = batch->intel;
@@ -255,7 +207,7 @@ intel_batchbuffer_flush(struct intel_batchbuffer *batch)
GLboolean was_locked = intel->locked;
if (used == 0)
return batch->last_fence;
return;
/* Add the MI_BATCH_BUFFER_END. Always add an MI_FLUSH - this is a
* performance drain that we would like to avoid.
@@ -272,10 +224,6 @@ intel_batchbuffer_flush(struct intel_batchbuffer *batch)
used += 8;
}
driBOUnmap(batch->buffer);
batch->ptr = NULL;
batch->map = NULL;
/* TODO: Just pass the relocation list and dma buffer up to the
* kernel.
*/
@@ -291,16 +239,14 @@ intel_batchbuffer_flush(struct intel_batchbuffer *batch)
/* Reset the buffer:
*/
intel_batchbuffer_reset(batch);
return batch->last_fence;
}
void
intel_batchbuffer_finish(struct intel_batchbuffer *batch)
{
struct _DriFenceObject *fence = intel_batchbuffer_flush(batch);
driFenceReference(fence);
driFenceFinish(fence, 3, GL_FALSE);
driFenceUnReference(fence);
intel_batchbuffer_flush(batch);
if (batch->last_fence != NULL)
dri_fence_wait(batch->last_fence);
}
@@ -308,20 +254,18 @@ intel_batchbuffer_finish(struct intel_batchbuffer *batch)
*/
GLboolean
intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
struct _DriBufferObject *buffer,
GLuint flags, GLuint mask, GLuint delta)
dri_bo *buffer,
GLuint flags, GLuint delta)
{
assert(batch->nr_relocs < MAX_RELOCS);
driBOAddListItem(&batch->list, buffer, flags, mask);
{
struct buffer_reloc *r = &batch->reloc[batch->nr_relocs++];
driBOReference(buffer);
assert(batch->nr_relocs <= MAX_RELOCS);
dri_bo_reference(buffer);
r->buf = buffer;
r->offset = batch->ptr - batch->map;
r->delta = delta;
}
r->validate_flags = flags;
batch->ptr += 4;
return GL_TRUE;

19
src/mesa/drivers/dri/i915tex/intel_batchbuffer.h
View File

@@ -16,9 +16,10 @@ struct intel_context;
struct buffer_reloc
{
struct _DriBufferObject *buf;
dri_bo *buf;
GLuint offset;
GLuint delta; /* not needed? */
GLuint validate_flags;
};
struct intel_batchbuffer
@@ -26,8 +27,8 @@ struct intel_batchbuffer
struct bufmgr *bm;
struct intel_context *intel;
struct _DriBufferObject *buffer;
struct _DriFenceObject *last_fence;
dri_bo *buf;
dri_fence *last_fence;
GLuint flags;
drmBOList list;
@@ -48,8 +49,7 @@ void intel_batchbuffer_free(struct intel_batchbuffer *batch);
void intel_batchbuffer_finish(struct intel_batchbuffer *batch);
struct _DriFenceObject *intel_batchbuffer_flush(struct intel_batchbuffer
*batch);
void intel_batchbuffer_flush(struct intel_batchbuffer *batch);
void intel_batchbuffer_reset(struct intel_batchbuffer *batch);
@@ -65,9 +65,8 @@ void intel_batchbuffer_release_space(struct intel_batchbuffer *batch,
GLuint bytes);
GLboolean intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
struct _DriBufferObject *buffer,
GLuint flags,
GLuint mask, GLuint offset);
dri_bo *buffer,
GLuint flags, GLuint offset);
/* Inline functions - might actually be better off with these
* non-inlined. Certainly better off switching all command packets to
@@ -113,9 +112,9 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
#define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d)
#define OUT_RELOC(buf,flags,mask,delta) do { \
#define OUT_RELOC(buf, flags, delta) do { \
assert((delta) >= 0); \
intel_batchbuffer_emit_reloc(intel->batch, buf, flags, mask, delta); \
intel_batchbuffer_emit_reloc(intel->batch, buf, flags, delta); \
} while (0)
#define ADVANCE_BATCH() do { } while(0)

418
src/mesa/drivers/dri/i915tex/intel_batchpool.c
View File

@@ -1,418 +0,0 @@
/**************************************************************************
*
* Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
*
**************************************************************************/
/*
* Authors: Thomas Hellstr<74>m <thomas-at-tungstengraphics-dot-com>
*/
#include <xf86drm.h>
#include <stdlib.h>
#include <errno.h>
#include "imports.h"
#include "glthread.h"
#include "dri_bufpool.h"
#include "dri_bufmgr.h"
#include "intel_screen.h"
typedef struct
{
drmMMListHead head;
struct _BPool *parent;
struct _DriFenceObject *fence;
unsigned long start;
int unfenced;
int mapped;
} BBuf;
typedef struct _BPool
{
_glthread_Mutex mutex;
unsigned long bufSize;
unsigned poolSize;
unsigned numFree;
unsigned numTot;
unsigned numDelayed;
unsigned checkDelayed;
drmMMListHead free;
drmMMListHead delayed;
drmMMListHead head;
drmBO kernelBO;
void *virtual;
BBuf *bufs;
} BPool;
static BPool *
createBPool(int fd, unsigned long bufSize, unsigned numBufs, unsigned flags,
unsigned checkDelayed)
{
BPool *p = (BPool *) malloc(sizeof(*p));
BBuf *buf;
int i;
if (!p)
return NULL;
p->bufs = (BBuf *) malloc(numBufs * sizeof(*p->bufs));
if (!p->bufs) {
free(p);
return NULL;
}
DRMINITLISTHEAD(&p->free);
DRMINITLISTHEAD(&p->head);
DRMINITLISTHEAD(&p->delayed);
p->numTot = numBufs;
p->numFree = numBufs;
p->bufSize = bufSize;
p->numDelayed = 0;
p->checkDelayed = checkDelayed;
_glthread_INIT_MUTEX(p->mutex);
if (drmBOCreate(fd, 0, numBufs * bufSize, 0, NULL, drm_bo_type_dc,
flags, 0, &p->kernelBO)) {
free(p->bufs);
free(p);
return NULL;
}
if (drmBOMap(fd, &p->kernelBO, DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0,
&p->virtual)) {
drmBODestroy(fd, &p->kernelBO);
free(p->bufs);
free(p);
return NULL;
}
/*
* We unmap the buffer so that we can validate it later. Note that this is
* just a synchronizing operation. The buffer will have a virtual mapping
* until it is destroyed.
*/
drmBOUnmap(fd, &p->kernelBO);
buf = p->bufs;
for (i = 0; i < numBufs; ++i) {
buf->parent = p;
buf->fence = NULL;
buf->start = i * bufSize;
buf->mapped = 0;
buf->unfenced = 0;
DRMLISTADDTAIL(&buf->head, &p->free);
buf++;
}
return p;
}
static void
pool_checkFree(BPool * p, int wait)
{
drmMMListHead *list, *prev;
BBuf *buf;
int signaled = 0;
int i;
list = p->delayed.next;
if (p->numDelayed > 3) {
for (i = 0; i < p->numDelayed; i += 3) {
list = list->next;
}
}
prev = list->prev;
for (; list != &p->delayed; list = prev, prev = list->prev) {
buf = DRMLISTENTRY(BBuf, list, head);
if (!signaled) {
if (wait) {
driFenceFinish(buf->fence, DRM_FENCE_TYPE_EXE, 1);
signaled = 1;
}
else {
signaled = driFenceSignaled(buf->fence, DRM_FENCE_TYPE_EXE);
}
}
if (!signaled)
break;
driFenceUnReference(buf->fence);
buf->fence = NULL;
DRMLISTDEL(list);
p->numDelayed--;
DRMLISTADD(list, &p->free);
p->numFree++;
}
}
static void *
pool_create(struct _DriBufferPool *pool,
unsigned long size, unsigned flags, unsigned hint,
unsigned alignment)
{
BPool *p = (BPool *) pool->data;
drmMMListHead *item;
if (alignment && (alignment != 4096))
return NULL;
_glthread_LOCK_MUTEX(p->mutex);
if (p->numFree == 0)
pool_checkFree(p, GL_TRUE);
if (p->numFree == 0) {
fprintf(stderr, "Out of fixed size buffer objects\n");
BM_CKFATAL(-ENOMEM);
}
item = p->free.next;
if (item == &p->free) {
fprintf(stderr, "Fixed size buffer pool corruption\n");
}
DRMLISTDEL(item);
--p->numFree;
_glthread_UNLOCK_MUTEX(p->mutex);
return (void *) DRMLISTENTRY(BBuf, item, head);
}
static int
pool_destroy(struct _DriBufferPool *pool, void *private)
{
BBuf *buf = (BBuf *) private;
BPool *p = buf->parent;
_glthread_LOCK_MUTEX(p->mutex);
if (buf->fence) {
DRMLISTADDTAIL(&buf->head, &p->delayed);
p->numDelayed++;
}
else {
buf->unfenced = 0;
DRMLISTADD(&buf->head, &p->free);
p->numFree++;
}
if ((p->numDelayed % p->checkDelayed) == 0)
pool_checkFree(p, 0);
_glthread_UNLOCK_MUTEX(p->mutex);
return 0;
}
static int
pool_map(struct _DriBufferPool *pool, void *private, unsigned flags,
int hint, void **virtual)
{
BBuf *buf = (BBuf *) private;
BPool *p = buf->parent;
_glthread_LOCK_MUTEX(p->mutex);
/*
* Currently Mesa doesn't have any condition variables to resolve this
* cleanly in a multithreading environment.
* We bail out instead.
*/
if (buf->mapped) {
fprintf(stderr, "Trying to map already mapped buffer object\n");
BM_CKFATAL(-EINVAL);
}
#if 0
if (buf->unfenced && !(hint & DRM_BO_HINT_ALLOW_UNFENCED_MAP)) {
fprintf(stderr, "Trying to map an unfenced buffer object 0x%08x"
" 0x%08x %d\n", hint, flags, buf->start);
BM_CKFATAL(-EINVAL);
}
#endif
if (buf->fence) {
_glthread_UNLOCK_MUTEX(p->mutex);
return -EBUSY;
}
buf->mapped = GL_TRUE;
*virtual = (unsigned char *) p->virtual + buf->start;
_glthread_UNLOCK_MUTEX(p->mutex);
return 0;
}
static int
pool_waitIdle(struct _DriBufferPool *pool, void *private, int lazy)
{
BBuf *buf = (BBuf *) private;
driFenceFinish(buf->fence, 0, lazy);
return 0;
}
static int
pool_unmap(struct _DriBufferPool *pool, void *private)
{
BBuf *buf = (BBuf *) private;
buf->mapped = 0;
return 0;
}
static unsigned long
pool_offset(struct _DriBufferPool *pool, void *private)
{
BBuf *buf = (BBuf *) private;
BPool *p = buf->parent;
return p->kernelBO.offset + buf->start;
}
static unsigned
pool_flags(struct _DriBufferPool *pool, void *private)
{
BPool *p = (BPool *) pool->data;
return p->kernelBO.flags;
}
static unsigned long
pool_size(struct _DriBufferPool *pool, void *private)
{
BPool *p = (BPool *) pool->data;
return p->bufSize;
}
static int
pool_fence(struct _DriBufferPool *pool, void *private,
struct _DriFenceObject *fence)
{
BBuf *buf = (BBuf *) private;
BPool *p = buf->parent;
_glthread_LOCK_MUTEX(p->mutex);
if (buf->fence) {
driFenceUnReference(buf->fence);
}
buf->fence = fence;
buf->unfenced = 0;
driFenceReference(buf->fence);
_glthread_UNLOCK_MUTEX(p->mutex);
return 0;
}
static drmBO *
pool_kernel(struct _DriBufferPool *pool, void *private)
{
BBuf *buf = (BBuf *) private;
BPool *p = buf->parent;
return &p->kernelBO;
}
static int
pool_validate(struct _DriBufferPool *pool, void *private)
{
BBuf *buf = (BBuf *) private;
BPool *p = buf->parent;
_glthread_LOCK_MUTEX(p->mutex);
buf->unfenced = GL_TRUE;
_glthread_UNLOCK_MUTEX(p->mutex);
return 0;
}
static void
pool_takedown(struct _DriBufferPool *pool)
{
BPool *p = (BPool *) pool->data;
/*
* Wait on outstanding fences.
*/
_glthread_LOCK_MUTEX(p->mutex);
while ((p->numFree < p->numTot) && p->numDelayed) {
_glthread_UNLOCK_MUTEX(p->mutex);
sched_yield();
pool_checkFree(p, GL_TRUE);
_glthread_LOCK_MUTEX(p->mutex);
}
drmBODestroy(pool->fd, &p->kernelBO);
free(p->bufs);
_glthread_UNLOCK_MUTEX(p->mutex);
free(p);
free(pool);
}
struct _DriBufferPool *
driBatchPoolInit(int fd, unsigned flags,
unsigned long bufSize,
unsigned numBufs, unsigned checkDelayed)
{
struct _DriBufferPool *pool;
pool = (struct _DriBufferPool *) malloc(sizeof(*pool));
if (!pool)
return NULL;
pool->data = createBPool(fd, bufSize, numBufs, flags, checkDelayed);
if (!pool->data)
return NULL;
pool->fd = fd;
pool->map = &pool_map;
pool->unmap = &pool_unmap;
pool->destroy = &pool_destroy;
pool->offset = &pool_offset;
pool->flags = &pool_flags;
pool->size = &pool_size;
pool->create = &pool_create;
pool->fence = &pool_fence;
pool->kernel = &pool_kernel;
pool->validate = &pool_validate;
pool->waitIdle = &pool_waitIdle;
pool->setstatic = NULL;
pool->takeDown = &pool_takedown;
return pool;
}

35
src/mesa/drivers/dri/i915tex/intel_blit.c
View File

@@ -67,8 +67,8 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
intelScreen = intel->intelScreen;
if (intel->last_swap_fence) {
driFenceFinish(intel->last_swap_fence, DRM_FENCE_TYPE_EXE, GL_TRUE);
driFenceUnReference(intel->last_swap_fence);
dri_fence_wait(intel->last_swap_fence);
dri_fence_unreference(intel->last_swap_fence);
intel->last_swap_fence = NULL;
}
intel->last_swap_fence = intel->first_swap_fence;
@@ -140,19 +140,20 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
OUT_BATCH((pbox->y2 << 16) | pbox->x2);
OUT_RELOC(frontRegion->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, 0);
0);
OUT_BATCH((pbox->y1 << 16) | pbox->x1);
OUT_BATCH(BR13 & 0xffff);
OUT_RELOC(backRegion->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, 0);
0);
ADVANCE_BATCH();
}
if (intel->first_swap_fence)
driFenceUnReference(intel->first_swap_fence);
intel->first_swap_fence = intel_batchbuffer_flush(intel->batch);
driFenceReference(intel->first_swap_fence);
dri_fence_unreference(intel->first_swap_fence);
intel_batchbuffer_flush(intel->batch);
dri_fence_reference(intel->first_swap_fence);
intel->first_swap_fence = intel->batch->last_fence;
}
UNLOCK_HARDWARE(intel);
@@ -165,7 +166,7 @@ void
intelEmitFillBlit(struct intel_context *intel,
GLuint cpp,
GLshort dst_pitch,
struct _DriBufferObject *dst_buffer,
dri_bo *dst_buffer,
GLuint dst_offset,
GLshort x, GLshort y, GLshort w, GLshort h, GLuint color)
{
@@ -199,8 +200,7 @@ intelEmitFillBlit(struct intel_context *intel,
OUT_BATCH(BR13);
OUT_BATCH((y << 16) | x);
OUT_BATCH(((y + h) << 16) | (x + w));
OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, dst_offset);
OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset);
OUT_BATCH(color);
ADVANCE_BATCH();
}
@@ -236,10 +236,10 @@ void
intelEmitCopyBlit(struct intel_context *intel,
GLuint cpp,
GLshort src_pitch,
struct _DriBufferObject *src_buffer,
dri_bo *src_buffer,
GLuint src_offset,
GLshort dst_pitch,
struct _DriBufferObject *dst_buffer,
dri_bo *dst_buffer,
GLuint dst_offset,
GLshort src_x, GLshort src_y,
GLshort dst_x, GLshort dst_y,
@@ -297,12 +297,10 @@ intelEmitCopyBlit(struct intel_context *intel,
OUT_BATCH(BR13);
OUT_BATCH((dst_y << 16) | dst_x);
OUT_BATCH((dst_y2 << 16) | dst_x2);
OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, dst_offset);
OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset);
OUT_BATCH((src_y << 16) | src_x);
OUT_BATCH(((GLint) src_pitch & 0xffff));
OUT_RELOC(src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, src_offset);
OUT_RELOC(src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, src_offset);
ADVANCE_BATCH();
}
else {
@@ -312,12 +310,10 @@ intelEmitCopyBlit(struct intel_context *intel,
OUT_BATCH((0 << 16) | dst_x);
OUT_BATCH((h << 16) | dst_x2);
OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
dst_offset + dst_y * dst_pitch);
OUT_BATCH((0 << 16) | src_x);
OUT_BATCH(((GLint) src_pitch & 0xffff));
OUT_RELOC(src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
DRM_BO_MASK_MEM | DRM_BO_FLAG_READ,
src_offset + src_y * src_pitch);
ADVANCE_BATCH();
}
@@ -420,7 +416,7 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
/* OK, clear this renderbuffer */
struct intel_region *irb_region =
intel_get_rb_region(fb, buf);
struct _DriBufferObject *write_buffer =
dri_bo *write_buffer =
intel_region_buffer(intel->intelScreen, irb_region,
all ? INTEL_WRITE_FULL :
INTEL_WRITE_PART);
@@ -483,7 +479,6 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask)
OUT_BATCH((b.y1 << 16) | b.x1);
OUT_BATCH((b.y2 << 16) | b.x2);
OUT_RELOC(write_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
irb_region->draw_offset);
OUT_BATCH(clearVal);
ADVANCE_BATCH();

6
src/mesa/drivers/dri/i915tex/intel_blit.h
View File

@@ -40,10 +40,10 @@ extern void intelClearWithBlit(GLcontext * ctx, GLbitfield mask);
extern void intelEmitCopyBlit(struct intel_context *intel,
GLuint cpp,
GLshort src_pitch,
struct _DriBufferObject *src_buffer,
dri_bo *src_buffer,
GLuint src_offset,
GLshort dst_pitch,
struct _DriBufferObject *dst_buffer,
dri_bo *dst_buffer,
GLuint dst_offset,
GLshort srcx, GLshort srcy,
GLshort dstx, GLshort dsty,
@@ -53,7 +53,7 @@ extern void intelEmitCopyBlit(struct intel_context *intel,
extern void intelEmitFillBlit(struct intel_context *intel,
GLuint cpp,
GLshort dst_pitch,
struct _DriBufferObject *dst_buffer,
dri_bo *dst_buffer,
GLuint dst_offset,
GLshort x, GLshort y,
GLshort w, GLshort h, GLuint color);

64
src/mesa/drivers/dri/i915tex/intel_buffer_objects.c
View File

@@ -35,6 +35,17 @@
#include "intel_regions.h"
#include "dri_bufmgr.h"
/** Allocates a new dri_bo to store the data for the buffer object. */
static void
intel_bufferobj_alloc_buffer(struct intel_context *intel,
struct intel_buffer_object *intel_obj)
{
intel_obj->buffer = dri_bo_alloc(intel->intelScreen->bufmgr, "bufferobj",
intel_obj->Base.Size, 64,
DRM_BO_FLAG_MEM_LOCAL |
DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0);
}
/**
* There is some duplication between mesa's bufferobjects and our
* bufmgr buffers. Both have an integer handle and a hashtable to
@@ -44,21 +55,15 @@
static struct gl_buffer_object *
intel_bufferobj_alloc(GLcontext * ctx, GLuint name, GLenum target)
{
struct intel_context *intel = intel_context(ctx);
struct intel_buffer_object *obj = CALLOC_STRUCT(intel_buffer_object);
_mesa_initialize_buffer_object(&obj->Base, name, target);
driGenBuffers(intel->intelScreen->regionPool,
"bufferobj", 1, &obj->buffer, 64,
DRM_BO_FLAG_MEM_LOCAL |
DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
0);
obj->buffer = NULL;
return &obj->Base;
}
/* Break the COW tie to the region. The region gets to keep the data.
*/
void
@@ -68,15 +73,9 @@ intel_bufferobj_release_region(struct intel_context *intel,
assert(intel_obj->region->buffer == intel_obj->buffer);
intel_obj->region->pbo = NULL;
intel_obj->region = NULL;
driBOUnReference(intel_obj->buffer);
intel_obj->buffer = NULL;
/* This leads to a large number of buffer deletion/creation events.
* Currently the drm doesn't like that:
*/
driGenBuffers(intel->intelScreen->regionPool,
"buffer object", 1, &intel_obj->buffer, 64, 0, 0);
driBOData(intel_obj->buffer, intel_obj->Base.Size, NULL, 0);
dri_bo_unreference(intel_obj->buffer);
intel_obj->buffer = NULL;
}
/* Break the COW tie to the region. Both the pbo and the region end
@@ -107,7 +106,7 @@ intel_bufferobj_free(GLcontext * ctx, struct gl_buffer_object *obj)
intel_bufferobj_release_region(intel, intel_obj);
}
else if (intel_obj->buffer) {
driDeleteBuffers(1, &intel_obj->buffer);
dri_bo_unreference(intel_obj->buffer);
}
_mesa_free(intel_obj);
@@ -137,7 +136,15 @@ intel_bufferobj_data(GLcontext * ctx,
if (intel_obj->region)
intel_bufferobj_release_region(intel, intel_obj);
driBOData(intel_obj->buffer, size, data, 0);
if (intel_obj->buffer != NULL && intel_obj->buffer->size != size) {
dri_bo_unreference(intel_obj->buffer);
intel_obj->buffer = NULL;
}
intel_bufferobj_alloc_buffer(intel, intel_obj);
if (data != NULL)
dri_bo_subdata(intel_obj->buffer, 0, size, data);
}
@@ -162,7 +169,7 @@ intel_bufferobj_subdata(GLcontext * ctx,
if (intel_obj->region)
intel_bufferobj_cow(intel, intel_obj);
driBOSubData(intel_obj->buffer, offset, size, data);
dri_bo_subdata(intel_obj->buffer, offset, size, data);
}
@@ -179,7 +186,7 @@ intel_bufferobj_get_subdata(GLcontext * ctx,
struct intel_buffer_object *intel_obj = intel_buffer_object(obj);
assert(intel_obj);
driBOGetSubData(intel_obj->buffer, offset, size, data);
dri_bo_subdata(intel_obj->buffer, offset, size, data);
}
@@ -202,8 +209,13 @@ intel_bufferobj_map(GLcontext * ctx,
if (intel_obj->region)
intel_bufferobj_cow(intel, intel_obj);
obj->Pointer = driBOMap(intel_obj->buffer,
DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0);
if (intel_obj->buffer == NULL) {
obj->Pointer = NULL;
return NULL;
}
dri_bo_map(intel_obj->buffer, GL_TRUE);
obj->Pointer = intel_obj->buffer->virtual;
return obj->Pointer;
}
@@ -218,21 +230,25 @@ intel_bufferobj_unmap(GLcontext * ctx,
struct intel_buffer_object *intel_obj = intel_buffer_object(obj);
assert(intel_obj);
if (intel_obj->buffer != NULL) {
assert(obj->Pointer);
driBOUnmap(intel_obj->buffer);
dri_bo_unmap(intel_obj->buffer);
obj->Pointer = NULL;
}
return GL_TRUE;
}
struct _DriBufferObject *
dri_bo *
intel_bufferobj_buffer(struct intel_context *intel,
struct intel_buffer_object *intel_obj, GLuint flag)
{
if (intel_obj->region) {
if (flag == INTEL_WRITE_PART)
intel_bufferobj_cow(intel, intel_obj);
else if (flag == INTEL_WRITE_FULL)
else if (flag == INTEL_WRITE_FULL) {
intel_bufferobj_release_region(intel, intel_obj);
intel_bufferobj_alloc_buffer(intel, intel_obj);
}
}
return intel_obj->buffer;

4
src/mesa/drivers/dri/i915tex/intel_buffer_objects.h
View File

@@ -41,7 +41,7 @@ struct gl_buffer_object;
struct intel_buffer_object
{
struct gl_buffer_object Base;
struct _DriBufferObject *buffer; /* the low-level buffer manager's buffer handle */
dri_bo *buffer; /* the low-level buffer manager's buffer handle */
struct intel_region *region; /* Is there a zero-copy texture
associated with this (pixel)
@@ -51,7 +51,7 @@ struct intel_buffer_object
/* Get the bm buffer associated with a GL bufferobject:
*/
struct _DriBufferObject *intel_bufferobj_buffer(struct intel_context *intel,
dri_bo *intel_bufferobj_buffer(struct intel_context *intel,
struct intel_buffer_object
*obj, GLuint flag);

18
src/mesa/drivers/dri/i915tex/intel_context.c
View File

@@ -303,9 +303,8 @@ intelFinish(GLcontext * ctx)
struct intel_context *intel = intel_context(ctx);
intelFlush(ctx);
if (intel->batch->last_fence) {
driFenceFinish(intel->batch->last_fence,
0, GL_FALSE);
driFenceUnReference(intel->batch->last_fence);
dri_fence_wait(intel->batch->last_fence);
dri_fence_unreference(intel->batch->last_fence);
intel->batch->last_fence = NULL;
}
intelCheckFrontRotate(ctx);
@@ -441,7 +440,6 @@ intelInitContext(struct intel_context *intel,
intel->RenderIndex = ~0;
fthrottle_mode = driQueryOptioni(&intel->optionCache, "fthrottle_mode");
intel->iw.irq_seq = -1;
intel->irqsEmitted = 0;
intel->do_irqs = (intel->intelScreen->irq_active &&
@@ -514,13 +512,13 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv)
intel_batchbuffer_free(intel->batch);
if (intel->last_swap_fence) {
driFenceFinish(intel->last_swap_fence, DRM_FENCE_TYPE_EXE, GL_TRUE);
driFenceUnReference(intel->last_swap_fence);
dri_fence_wait(intel->last_swap_fence);
dri_fence_unreference(intel->last_swap_fence);
intel->last_swap_fence = NULL;
}
if (intel->first_swap_fence) {
driFenceFinish(intel->first_swap_fence, DRM_FENCE_TYPE_EXE, GL_TRUE);
driFenceUnReference(intel->first_swap_fence);
dri_fence_wait(intel->first_swap_fence);
dri_fence_unreference(intel->first_swap_fence);
intel->first_swap_fence = NULL;
}
@@ -664,14 +662,14 @@ intelContendedLock(struct intel_context *intel, GLuint flags)
*/
if (batchMap != NULL) {
driBOUnmap(intel->batch->buffer);
dri_bo_unmap(intel->batch->buf);
intel->batch->map = NULL;
}
intel_batchbuffer_reset(intel->batch);
if (batchMap == NULL) {
driBOUnmap(intel->batch->buffer);
dri_bo_unmap(intel->batch->buf);
intel->batch->map = NULL;
}

8
src/mesa/drivers/dri/i915tex/intel_context.h
View File

@@ -50,7 +50,6 @@
struct intel_region;
struct intel_context;
struct _DriBufferObject;
typedef void (*intel_tri_func) (struct intel_context *, intelVertex *,
intelVertex *, intelVertex *);
@@ -165,7 +164,7 @@ struct intel_context
void (*meta_import_pixel_state) (struct intel_context * intel);
GLboolean(*meta_tex_rect_source) (struct intel_context * intel,
struct _DriBufferObject * buffer,
dri_bo * buffer,
GLuint offset,
GLuint pitch,
GLuint height,
@@ -181,8 +180,8 @@ struct intel_context
GLuint Fallback;
GLuint NewGLState;
struct _DriFenceObject *last_swap_fence;
struct _DriFenceObject *first_swap_fence;
dri_fence *last_swap_fence;
dri_fence *first_swap_fence;
struct intel_batchbuffer *batch;
@@ -256,7 +255,6 @@ struct intel_context
GLuint do_usleeps;
int do_irqs;
GLuint irqsEmitted;
drm_i915_irq_wait_t iw;
drm_context_t hHWContext;
drmLock *driHwLock;

19
src/mesa/drivers/dri/i915tex/intel_ioctl.c
View File

@@ -45,18 +45,15 @@
#define FILE_DEBUG_FLAG DEBUG_IOCTL
int
intelEmitIrqLocked(struct intel_context *intel)
intelEmitIrqLocked(intelScreenPrivate *intelScreen)
{
drmI830IrqEmit ie;
int ret, seq;
assert(((*(int *) intel->driHwLock) & ~DRM_LOCK_CONT) ==
(DRM_LOCK_HELD | intel->hHWContext));
ie.irq_seq = &seq;
ret = drmCommandWriteRead(intel->driFd, DRM_I830_IRQ_EMIT,
&ie, sizeof(ie));
ret = drmCommandWriteRead(intelScreen->driScrnPriv->fd,
DRM_I830_IRQ_EMIT, &ie, sizeof(ie));
if (ret) {
fprintf(stderr, "%s: drmI830IrqEmit: %d\n", __FUNCTION__, ret);
exit(1);
@@ -68,18 +65,18 @@ intelEmitIrqLocked(struct intel_context *intel)
}
void
intelWaitIrq(struct intel_context *intel, int seq)
intelWaitIrq(intelScreenPrivate *intelScreen, int seq)
{
drm_i915_irq_wait_t iw;
int ret;
DBG("%s %d\n", __FUNCTION__, seq);
intel->iw.irq_seq = seq;
iw.irq_seq = seq;
do {
ret =
drmCommandWrite(intel->driFd, DRM_I830_IRQ_WAIT, &intel->iw,
sizeof(intel->iw));
ret = drmCommandWrite(intelScreen->driScrnPriv->fd,
DRM_I830_IRQ_WAIT, &iw, sizeof(iw));
} while (ret == -EAGAIN || ret == -EINTR);
if (ret) {

4
src/mesa/drivers/dri/i915tex/intel_ioctl.h
View File

@@ -30,8 +30,8 @@
#include "intel_context.h"
void intelWaitIrq(struct intel_context *intel, int seq);
int intelEmitIrqLocked(struct intel_context *intel);
void intelWaitIrq(intelScreenPrivate *intelScreen, int seq);
int intelEmitIrqLocked(intelScreenPrivate *intelScreen);
void intel_batch_ioctl(struct intel_context *intel,
GLuint start_offset,

14
src/mesa/drivers/dri/i915tex/intel_pixel_draw.c
View File

@@ -217,7 +217,7 @@ do_blit_drawpixels(GLcontext * ctx,
struct intel_buffer_object *src = intel_buffer_object(unpack->BufferObj);
GLuint src_offset;
GLuint rowLength;
struct _DriFenceObject *fence = NULL;
dri_fence *fence = NULL;
if (INTEL_DEBUG & DEBUG_PIXEL)
_mesa_printf("%s\n", __FUNCTION__);
@@ -298,8 +298,7 @@ do_blit_drawpixels(GLcontext * ctx,
drm_clip_rect_t *box = dPriv->pClipRects;
drm_clip_rect_t rect;
drm_clip_rect_t dest_rect;
struct _DriBufferObject *src_buffer =
intel_bufferobj_buffer(intel, src, INTEL_READ);
dri_bo *src_buffer = intel_bufferobj_buffer(intel, src, INTEL_READ);
int i;
dest_rect.x1 = dPriv->x + x;
@@ -324,14 +323,15 @@ do_blit_drawpixels(GLcontext * ctx,
ctx->Color.ColorLogicOpEnabled ?
ctx->Color.LogicOp : GL_COPY);
}
fence = intel_batchbuffer_flush(intel->batch);
driFenceReference(fence);
intel_batchbuffer_flush(intel->batch);
fence = intel->batch->last_fence;
dri_fence_reference(fence);
}
UNLOCK_HARDWARE(intel);
if (fence) {
driFenceFinish(fence, DRM_FENCE_TYPE_EXE | DRM_I915_FENCE_TYPE_RW, GL_FALSE);
driFenceUnReference(fence);
dri_fence_wait(fence);
dri_fence_unreference(fence);
}
if (INTEL_DEBUG & DEBUG_PIXEL)

16
src/mesa/drivers/dri/i915tex/intel_pixel_read.c
View File

@@ -173,7 +173,7 @@ do_blit_readpixels(GLcontext * ctx,
struct intel_buffer_object *dst = intel_buffer_object(pack->BufferObj);
GLuint dst_offset;
GLuint rowLength;
struct _DriFenceObject *fence = NULL;
dri_fence *fence = NULL;
if (INTEL_DEBUG & DEBUG_PIXEL)
_mesa_printf("%s\n", __FUNCTION__);
@@ -241,8 +241,8 @@ do_blit_readpixels(GLcontext * ctx,
GLboolean all = (width * height * src->cpp == dst->Base.Size &&
x == 0 && dst_offset == 0);
struct _DriBufferObject *dst_buffer =
intel_bufferobj_buffer(intel, dst, all ? INTEL_WRITE_FULL :
dri_bo *dst_buffer = intel_bufferobj_buffer(intel, dst,
all ? INTEL_WRITE_FULL :
INTEL_WRITE_PART);
__DRIdrawablePrivate *dPriv = intel->driDrawable;
int nbox = dPriv->numClipRects;
@@ -275,16 +275,16 @@ do_blit_readpixels(GLcontext * ctx,
GL_COPY);
}
fence = intel_batchbuffer_flush(intel->batch);
driFenceReference(fence);
intel_batchbuffer_flush(intel->batch);
fence = intel->batch->last_fence;
dri_fence_reference(fence);
}
UNLOCK_HARDWARE(intel);
if (fence) {
driFenceFinish(fence, DRM_FENCE_TYPE_EXE | DRM_I915_FENCE_TYPE_RW,
GL_FALSE);
driFenceUnReference(fence);
dri_fence_wait(fence);
dri_fence_unreference(fence);
}
if (INTEL_DEBUG & DEBUG_PIXEL)

86
src/mesa/drivers/dri/i915tex/intel_regions.c
View File

@@ -52,8 +52,17 @@ void
intel_region_idle(intelScreenPrivate *intelScreen, struct intel_region *region)
{
DBG("%s\n", __FUNCTION__);
if (region && region->buffer)
driBOWaitIdle(region->buffer, GL_FALSE);
/* XXX: Using this function is likely bogus -- it ought to only have been
* used before a map, anyway, but leave this cheap implementation of it
* for now.
*/
if (region && region->buffer) {
/* Mapping it for read will ensure that any acceleration to the region
* would have landed already.
*/
dri_bo_map(region->buffer, GL_TRUE);
dri_bo_unmap(region->buffer);
}
}
/* XXX: Thread safety?
@@ -66,8 +75,8 @@ intel_region_map(intelScreenPrivate *intelScreen, struct intel_region *region)
if (region->pbo)
intel_region_cow(intelScreen, region);
region->map = driBOMap(region->buffer,
DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0);
dri_bo_map(region->buffer, GL_TRUE);
region->map = region->buffer->virtual;
}
return region->map;
@@ -78,13 +87,11 @@ intel_region_unmap(intelScreenPrivate *intelScreen, struct intel_region *region)
{
DBG("%s\n", __FUNCTION__);
if (!--region->map_refcount) {
driBOUnmap(region->buffer);
dri_bo_unmap(region->buffer);
region->map = NULL;
}
}
#undef TEST_CACHED_TEXTURES
struct intel_region *
intel_region_alloc(intelScreenPrivate *intelScreen,
GLuint cpp, GLuint pitch, GLuint height)
@@ -98,16 +105,8 @@ intel_region_alloc(intelScreenPrivate *intelScreen,
region->height = height; /* needed? */
region->refcount = 1;
driGenBuffers(intelScreen->regionPool,
"region", 1, &region->buffer, 64,
#ifdef TEST_CACHED_TEXTURES
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_BIND_CACHED |
DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
#else
0,
#endif
0);
driBOData(region->buffer, pitch * cpp * height, NULL, 0);
region->buffer = dri_bo_alloc(intelScreen->bufmgr, "region",
pitch * cpp * height, 64, 0, 0);
return region;
}
@@ -138,7 +137,7 @@ intel_region_release(struct intel_region **region)
if ((*region)->pbo)
(*region)->pbo->region = NULL;
(*region)->pbo = NULL;
driBOUnReference((*region)->buffer);
dri_bo_unreference((*region)->buffer);
free(*region);
}
*region = NULL;
@@ -160,16 +159,13 @@ intel_region_create_static(intelScreenPrivate *intelScreen,
region->height = height; /* needed? */
region->refcount = 1;
/*
* We use a "shared" buffer type to indicate buffers created and
* shared by others.
*/
driGenBuffers(intelScreen->staticPool, "static region", 1,
&region->buffer, 64,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_NO_MOVE |
DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0);
driBOSetStatic(region->buffer, offset, pitch * cpp * height, virtual, 0);
/* XXX: questionable flags */
region->buffer = dri_bo_alloc_static(intelScreen->bufmgr, "static region",
offset, pitch * cpp * height, virtual,
DRM_BO_FLAG_MEM_TT |
DRM_BO_FLAG_NO_MOVE |
DRM_BO_FLAG_READ |
DRM_BO_FLAG_WRITE, 0);
return region;
}
@@ -195,13 +191,14 @@ intel_region_update_static(intelScreenPrivate *intelScreen,
* shared by others.
*/
driDeleteBuffers(1, &region->buffer);
driGenBuffers(intelScreen->staticPool, "static region", 1,
&region->buffer, 64,
DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_NO_MOVE |
DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0);
driBOSetStatic(region->buffer, offset, pitch * cpp * height, virtual, 0);
dri_bo_unreference(region->buffer);
/* XXX: questionable flags */
region->buffer = dri_bo_alloc_static(intelScreen->bufmgr, "static region",
offset, pitch * cpp * height, virtual,
DRM_BO_FLAG_MEM_TT |
DRM_BO_FLAG_NO_MOVE |
DRM_BO_FLAG_READ |
DRM_BO_FLAG_WRITE, 0);
}
@@ -376,17 +373,19 @@ intel_region_attach_pbo(intelScreenPrivate *intelScreen,
}
if (region->buffer) {
driDeleteBuffers(1, &region->buffer);
dri_bo_unreference(region->buffer);
region->buffer = NULL;
}
region->pbo = pbo;
region->pbo->region = region;
region->buffer = driBOReference(pbo->buffer);
dri_bo_reference(pbo->buffer);
region->buffer = pbo->buffer;
}
/* Break the COW tie to the pbo. The pbo gets to keep the data.
/* Break the COW tie to the pbo and allocate a new buffer.
* The pbo gets to keep the data.
*/
void
intel_region_release_pbo(intelScreenPrivate *intelScreen,
@@ -395,13 +394,12 @@ intel_region_release_pbo(intelScreenPrivate *intelScreen,
assert(region->buffer == region->pbo->buffer);
region->pbo->region = NULL;
region->pbo = NULL;
driBOUnReference(region->buffer);
dri_bo_unreference(region->buffer);
region->buffer = NULL;
driGenBuffers(intelScreen->regionPool,
"region", 1, &region->buffer, 64, 0, 0);
driBOData(region->buffer,
region->cpp * region->pitch * region->height, NULL, 0);
region->buffer = dri_bo_alloc(intelScreen->bufmgr, "region",
region->pitch * region->cpp * region->height,
64, 0, 0);
}
/* Break the COW tie to the pbo. Both the pbo and the region end up
@@ -457,7 +455,7 @@ intel_region_cow(intelScreenPrivate *intelScreen, struct intel_region *region)
}
}
struct _DriBufferObject *
dri_bo *
intel_region_buffer(intelScreenPrivate *intelScreen,
struct intel_region *region, GLuint flag)
{

4
src/mesa/drivers/dri/i915tex/intel_regions.h
View File

@@ -44,7 +44,7 @@ struct intel_buffer_object;
*/
struct intel_region
{
struct _DriBufferObject *buffer; /**< buffer manager's buffer ID */
dri_bo *buffer; /**< buffer manager's buffer */
GLuint refcount; /**< Reference count for region */
GLuint cpp; /**< bytes per pixel */
GLuint pitch; /**< in pixels */
@@ -134,7 +134,7 @@ void intel_region_release_pbo(intelScreenPrivate *intelScreen,
void intel_region_cow(intelScreenPrivate *intelScreen,
struct intel_region *region);
struct _DriBufferObject *intel_region_buffer(intelScreenPrivate *intelScreen,
dri_bo *intel_region_buffer(intelScreenPrivate *intelScreen,
struct intel_region *region,
GLuint flag);

98
src/mesa/drivers/dri/i915tex/intel_screen.c
View File

@@ -46,7 +46,7 @@
#include "intel_fbo.h"
#include "i830_dri.h"
#include "dri_bufpool.h"
#include "dri_bufmgr.h"
#include "intel_regions.h"
#include "intel_batchbuffer.h"
@@ -120,8 +120,11 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv)
return GL_FALSE;
}
#if 0
if (0)
_mesa_printf("TEX 0x%08x ", intelScreen->tex.handle);
if (intelScreen->tex.size != 0) {
intelScreen->ttm = GL_FALSE;
if (drmMap(sPriv->fd,
intelScreen->tex.handle,
intelScreen->tex.size,
@@ -129,7 +132,10 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv)
intelUnmapScreenRegions(intelScreen);
return GL_FALSE;
}
#endif
} else {
intelScreen->ttm = GL_TRUE;
}
if (0)
printf("Mappings: front: %p back: %p third: %p depth: %p tex: %p\n",
intelScreen->front.map,
@@ -138,6 +144,32 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv)
return GL_TRUE;
}
/** Driver-specific fence emit implementation for the fake memory manager. */
static unsigned int
intel_fence_emit(void *private)
{
intelScreenPrivate *intelScreen = (intelScreenPrivate *)private;
unsigned int fence;
/* XXX: Need to emit a flush, if we haven't already (at least with the
* current batchbuffer implementation, we have).
*/
fence = intelEmitIrqLocked(intelScreen);
return fence;
}
/** Driver-specific fence wait implementation for the fake memory manager. */
static int
intel_fence_wait(void *private, unsigned int cookie)
{
intelScreenPrivate *intelScreen = (intelScreenPrivate *)private;
intelWaitIrq(intelScreen, cookie);
return 0;
}
static struct intel_region *
intel_recreate_static(intelScreenPrivate *intelScreen,
@@ -393,7 +425,6 @@ intelInitDriver(__DRIscreenPrivate * sPriv)
intelScreenPrivate *intelScreen;
I830DRIPtr gDRIPriv = (I830DRIPtr) sPriv->pDevPriv;
drmI830Sarea *sarea;
unsigned batchPoolSize = 1024*1024;
PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
(PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->
@@ -422,11 +453,11 @@ intelInitDriver(__DRIscreenPrivate * sPriv)
sarea = (drmI830Sarea *)
(((GLubyte *) sPriv->pSAREA) + intelScreen->sarea_priv_offset);
intelScreen->maxBatchSize = BATCH_SZ;
intelScreen->deviceID = gDRIPriv->deviceID;
if (intelScreen->deviceID == PCI_CHIP_I865_G)
intelScreen->maxBatchSize = 4096;
batchPoolSize /= intelScreen->maxBatchSize;
else
intelScreen->maxBatchSize = BATCH_SZ;
intelScreen->mem = gDRIPriv->mem;
intelScreen->cpp = gDRIPriv->cpp;
@@ -452,24 +483,6 @@ intelInitDriver(__DRIscreenPrivate * sPriv)
return GL_FALSE;
}
#if 0
/*
* FIXME: Remove this code and its references.
*/
intelScreen->tex.offset = gDRIPriv->textureOffset;
intelScreen->logTextureGranularity = gDRIPriv->logTextureGranularity;
intelScreen->tex.handle = gDRIPriv->textures;
intelScreen->tex.size = gDRIPriv->textureSize;
#else
intelScreen->tex.offset = 0;
intelScreen->logTextureGranularity = 0;
intelScreen->tex.handle = 0;
intelScreen->tex.size = 0;
#endif
intelScreen->sarea_priv_offset = gDRIPriv->sarea_priv_offset;
if (0)
@@ -517,27 +530,18 @@ intelInitDriver(__DRIscreenPrivate * sPriv)
(*glx_enable_extension) (psc, "GLX_SGI_make_current_read");
}
intelScreen->regionPool = driDRMPoolInit(sPriv->fd);
if (!intelScreen->regionPool)
return GL_FALSE;
intelScreen->staticPool = driDRMStaticPoolInit(sPriv->fd);
if (!intelScreen->staticPool)
return GL_FALSE;
intelScreen->texPool = intelScreen->regionPool;
intelScreen->batchPool = driBatchPoolInit(sPriv->fd,
DRM_BO_FLAG_EXE |
DRM_BO_FLAG_MEM_TT |
DRM_BO_FLAG_MEM_LOCAL,
intelScreen->maxBatchSize,
batchPoolSize, 5);
if (!intelScreen->batchPool) {
fprintf(stderr, "Failed to initialize batch pool - possible incorrect agpgart installed\n");
return GL_FALSE;
if (intelScreen->ttm) {
intelScreen->bufmgr = dri_bufmgr_ttm_init(sPriv->fd,
DRM_FENCE_TYPE_EXE,
DRM_FENCE_TYPE_EXE |
DRM_I915_FENCE_TYPE_RW);
} else {
intelScreen->bufmgr = dri_bufmgr_fake_init(intelScreen->tex.offset,
intelScreen->tex.map,
intelScreen->tex.size,
intel_fence_emit,
intel_fence_wait,
intelScreen);
}
intel_recreate_static_regions(intelScreen);
@@ -553,9 +557,7 @@ intelDestroyScreen(__DRIscreenPrivate * sPriv)
intelUnmapScreenRegions(intelScreen);
driPoolTakeDown(intelScreen->regionPool);
driPoolTakeDown(intelScreen->staticPool);
driPoolTakeDown(intelScreen->batchPool);
/* XXX: bufmgr teardown */
FREE(intelScreen);
sPriv->private = NULL;
}

19
src/mesa/drivers/dri/i915tex/intel_screen.h
View File

@@ -33,7 +33,7 @@
#include "intel_rotate.h"
#include "i830_common.h"
#include "xmlconfig.h"
#include "dri_bufpool.h"
#include "dri_bufmgr.h"
/* XXX: change name or eliminate to avoid conflict with "struct
* intel_region"!!!
@@ -90,11 +90,15 @@ typedef struct
* Configuration cache with default values for all contexts
*/
driOptionCache optionCache;
struct _DriBufferPool *batchPool;
struct _DriBufferPool *texPool;
struct _DriBufferPool *regionPool;
struct _DriBufferPool *staticPool;
dri_bufmgr *bufmgr;
unsigned int maxBatchSize;
/**
* This value indicates that the kernel memory manager is being used
* instead of the fake client-side memory manager.
*/
GLboolean ttm;
} intelScreenPrivate;
@@ -121,11 +125,6 @@ extern void intelSwapBuffers(__DRIdrawablePrivate * dPriv);
extern void
intelCopySubBuffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h);
extern struct _DriBufferPool *driBatchPoolInit(int fd, unsigned flags,
unsigned long bufSize,
unsigned numBufs,
unsigned checkDelayed);
extern struct intel_context *intelScreenContext(intelScreenPrivate *intelScreen);
extern void

7
src/mesa/drivers/dri/i915tex/intel_tex_image.c
View File

@@ -221,10 +221,9 @@ try_pbo_upload(struct intel_context *intel,
intelFlush(&intel->ctx);
LOCK_HARDWARE(intel);
{
struct _DriBufferObject *src_buffer =
intel_bufferobj_buffer(intel, pbo, INTEL_READ);
struct _DriBufferObject *dst_buffer =
intel_region_buffer(intel->intelScreen, intelImage->mt->region,
dri_bo *src_buffer = intel_bufferobj_buffer(intel, pbo, INTEL_READ);
dri_bo *dst_buffer = intel_region_buffer(intel->intelScreen,
intelImage->mt->region,
INTEL_WRITE_FULL);

2
src/mesa/drivers/dri/i965/intel_context.c
View File

@@ -700,8 +700,6 @@ void UNLOCK_HARDWARE( struct intel_context *intel )
intel->vtbl.note_unlock( intel );
intel->locked = 0;
DRM_UNLOCK(intel->driFd, intel->driHwLock, intel->hHWContext);
_glthread_UNLOCK_MUTEX(lockMutex);
}