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radv: align the LDS size in calculate_tess_lds_size()

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5837>
This commit is contained in:
Samuel Pitoiset
2020-07-09 10:06:43 +02:00
committed by Marge Bot
parent 9c36ebf30e
commit cf89bdb9ba
4 changed files with 23 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/amd/compiler/aco_instruction_selection_setup.cpp
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@@ -1184,6 +1184,7 @@ setup_tcs_info(isel_context *ctx, nir_shader *nir, nir_shader *vs)
ctx->args->options->chip_class, ctx->args->options->chip_class,
ctx->args->options->family); ctx->args->options->family);
unsigned lds_size = calculate_tess_lds_size( unsigned lds_size = calculate_tess_lds_size(
ctx->args->options->chip_class,
ctx->args->options->key.tcs.input_vertices, ctx->args->options->key.tcs.input_vertices,
nir->info.tess.tcs_vertices_out, nir->info.tess.tcs_vertices_out,
ctx->tcs_num_inputs, ctx->tcs_num_inputs,
@@ -1192,7 +1193,7 @@ setup_tcs_info(isel_context *ctx, nir_shader *nir, nir_shader *vs)
ctx->tcs_num_patch_outputs); ctx->tcs_num_patch_outputs);
ctx->args->shader_info->tcs.num_patches = ctx->tcs_num_patches; ctx->args->shader_info->tcs.num_patches = ctx->tcs_num_patches;
ctx->args->shader_info->tcs.lds_size = lds_size; ctx->args->shader_info->tcs.num_lds_blocks = lds_size;
ctx->program->config->lds_size = (lds_size + ctx->program->lds_alloc_granule - 1) / ctx->program->config->lds_size = (lds_size + ctx->program->lds_alloc_granule - 1) /
ctx->program->lds_alloc_granule; ctx->program->lds_alloc_granule;
} }

3
src/amd/vulkan/radv_nir_to_llvm.c
View File

@@ -4142,8 +4142,9 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
unsigned tcs_num_outputs = util_last_bit64(ctx.args->shader_info->tcs.outputs_written); unsigned tcs_num_outputs = util_last_bit64(ctx.args->shader_info->tcs.outputs_written);
unsigned tcs_num_patch_outputs = util_last_bit64(ctx.args->shader_info->tcs.patch_outputs_written); unsigned tcs_num_patch_outputs = util_last_bit64(ctx.args->shader_info->tcs.patch_outputs_written);
args->shader_info->tcs.num_patches = ctx.tcs_num_patches; args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
args->shader_info->tcs.lds_size = args->shader_info->tcs.num_lds_blocks =
calculate_tess_lds_size( calculate_tess_lds_size(
ctx.args->options->chip_class,
ctx.args->options->key.tcs.input_vertices, ctx.args->options->key.tcs.input_vertices,
ctx.shader->info.tess.tcs_vertices_out, ctx.shader->info.tess.tcs_vertices_out,
ctx.tcs_num_inputs, ctx.tcs_num_inputs,

21
src/amd/vulkan/radv_pipeline.c
View File

@@ -84,7 +84,7 @@ struct radv_dsa_order_invariance {
struct radv_tessellation_state { struct radv_tessellation_state {
uint32_t ls_hs_config; uint32_t ls_hs_config;
unsigned lds_size; unsigned num_lds_blocks;
uint32_t tf_param; uint32_t tf_param;
}; };
@@ -1991,7 +1991,6 @@ calculate_tess_state(struct radv_pipeline *pipeline,
{ {
unsigned num_tcs_input_cp; unsigned num_tcs_input_cp;
unsigned num_tcs_output_cp; unsigned num_tcs_output_cp;
unsigned lds_size;
unsigned num_patches; unsigned num_patches;
struct radv_tessellation_state tess = {0}; struct radv_tessellation_state tess = {0};
@@ -1999,17 +1998,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size; tess.num_lds_blocks = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
assert(lds_size <= 65536);
lds_size = align(lds_size, 512) / 512;
} else {
assert(lds_size <= 32768);
lds_size = align(lds_size, 256) / 256;
}
tess.lds_size = lds_size;
tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) | tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) | S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
@@ -3918,7 +3907,7 @@ radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
radeon_emit(cs, va >> 8); radeon_emit(cs, va >> 8);
radeon_emit(cs, S_00B524_MEM_BASE(va >> 40)); radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size); rsrc2 |= S_00B52C_LDS_SIZE(tess->num_lds_blocks);
if (pipeline->device->physical_device->rad_info.chip_class == GFX7 && if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
pipeline->device->physical_device->rad_info.family != CHIP_HAWAII) pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2); radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
@@ -4074,9 +4063,9 @@ radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
unsigned hs_rsrc2 = shader->config.rsrc2; unsigned hs_rsrc2 = shader->config.rsrc2;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size); hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->num_lds_blocks);
} else { } else {
hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size); hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->num_lds_blocks);
} }
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {

17
src/amd/vulkan/radv_shader.h
View File

@@ -331,7 +331,7 @@ struct radv_shader_info {
uint64_t tes_patch_inputs_read; uint64_t tes_patch_inputs_read;
unsigned tcs_vertices_out; unsigned tcs_vertices_out;
uint32_t num_patches; uint32_t num_patches;
uint32_t lds_size; uint32_t num_lds_blocks;
uint8_t num_linked_inputs; uint8_t num_linked_inputs;
uint8_t num_linked_outputs; uint8_t num_linked_outputs;
uint8_t num_linked_patch_outputs; uint8_t num_linked_patch_outputs;
@@ -533,7 +533,8 @@ shader_io_get_unique_index(gl_varying_slot slot)
} }
static inline unsigned static inline unsigned
calculate_tess_lds_size(unsigned tcs_num_input_vertices, calculate_tess_lds_size(enum chip_class chip_class,
unsigned tcs_num_input_vertices,
unsigned tcs_num_output_vertices, unsigned tcs_num_output_vertices,
unsigned tcs_num_inputs, unsigned tcs_num_inputs,
unsigned tcs_num_patches, unsigned tcs_num_patches,
@@ -550,7 +551,17 @@ calculate_tess_lds_size(unsigned tcs_num_input_vertices,
unsigned output_patch0_offset = input_patch_size * tcs_num_patches; unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
return output_patch0_offset + output_patch_size * tcs_num_patches; unsigned lds_size = output_patch0_offset + output_patch_size * tcs_num_patches;
if (chip_class >= GFX7) {
assert(lds_size <= 65536);
lds_size = align(lds_size, 512) / 512;
} else {
assert(lds_size <= 32768);
lds_size = align(lds_size, 256) / 256;
}
return lds_size;
} }
static inline unsigned static inline unsigned