radv: introduce RADV_DEBUG=nofmask

To disable MSAA compression on MSAA images. This will also allow us to
emulate GFX11 (FMASK has been removed) and to experiment 32 byte
descriptor sizes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19613>

docs/envvars.rst

@@ -924,6 +924,8 @@ RADV driver environment variables
       do not check OOB access for dynamic descriptors
    ``nofastclears``
       disable fast color/depthstencil clears
+   ``nofmask``
+      disable FMASK compression on MSAA images (GFX6-GFX10.3)
    ``nohiz``
       disable HIZ for depthstencil images
    ``noibs``

src/amd/vulkan/radv_debug.h

@@ -67,6 +67,7 @@ enum {
    RADV_DEBUG_NO_DMA_BLIT = 1ull << 36,
    RADV_DEBUG_SPLIT_FMA = 1ull << 37,
    RADV_DEBUG_DUMP_EPILOGS = 1ull << 38,
+   RADV_DEBUG_NO_FMASK = 1ull << 39,
 };
 
 enum {

src/amd/vulkan/radv_device.c

@@ -629,7 +629,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device
       .AMD_shader_core_properties2 = true,
       /* TODO: Figure out if it's possible to implement it on gfx11. */
       .AMD_shader_explicit_vertex_parameter = device->rad_info.gfx_level < GFX11,
-      .AMD_shader_fragment_mask = device->rad_info.gfx_level < GFX11,
+      .AMD_shader_fragment_mask = device->use_fmask,
       .AMD_shader_image_load_store_lod = true,
       .AMD_shader_trinary_minmax = true,
       .AMD_texture_gather_bias_lod = device->rad_info.gfx_level < GFX11,
@@ -860,6 +860,9 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm
 
    device->dcc_msaa_allowed = (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
 
+   device->use_fmask = device->rad_info.gfx_level < GFX11 &&
+                       !(device->instance->debug_flags & RADV_DEBUG_NO_FMASK);
+
    device->use_ngg = (device->rad_info.gfx_level >= GFX10 &&
                      device->rad_info.family != CHIP_NAVI14 &&
                      !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) ||
@@ -1044,6 +1047,7 @@ static const struct debug_control radv_debug_options[] = {
    {"prologs", RADV_DEBUG_DUMP_PROLOGS},
    {"nodma", RADV_DEBUG_NO_DMA_BLIT},
    {"epilogs", RADV_DEBUG_DUMP_EPILOGS},
+   {"nofmask", RADV_DEBUG_NO_FMASK},
    {NULL, 0}};
 
 const char *

src/amd/vulkan/radv_image.c

@@ -336,8 +336,9 @@ radv_image_use_dcc_predication(const struct radv_device *device, const struct ra
 static inline bool
 radv_use_fmask_for_image(const struct radv_device *device, const struct radv_image *image)
 {
-   return image->info.samples > 1 && ((image->vk.usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) ||
+   return device->physical_device->use_fmask && image->info.samples > 1 &&
-                                      (device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS));
+          ((image->vk.usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) ||
+           (device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS));
 }
 
 static inline bool

src/amd/vulkan/radv_meta.c

@@ -456,7 +456,7 @@ radv_device_init_meta(struct radv_device *device)
    if (result != VK_SUCCESS)
       goto fail_resolve_fragment;
 
-   if (device->physical_device->rad_info.gfx_level < GFX11) {
+   if (device->physical_device->use_fmask) {
       result = radv_device_init_meta_fmask_expand_state(device);
       if (result != VK_SUCCESS)
          goto fail_fmask_expand;
@@ -597,9 +597,9 @@ radv_meta_build_nir_fs_noop(struct radv_device *dev)
 }
 
 void
-radv_meta_build_resolve_shader_core(nir_builder *b, bool is_integer, int samples,
+radv_meta_build_resolve_shader_core(struct radv_device *device, nir_builder *b, bool is_integer,
-                                    nir_variable *input_img, nir_variable *color,
+                                    int samples, nir_variable *input_img, nir_variable *color,
-                                    nir_ssa_def *img_coord, enum amd_gfx_level gfx_level)
+                                    nir_ssa_def *img_coord)
 {
    /* do a txf_ms on each sample */
    nir_ssa_def *tmp;
@@ -629,7 +629,7 @@ radv_meta_build_resolve_shader_core(nir_builder *b, bool is_integer, int samples
       return;
    }
 
-   if (gfx_level < GFX11) {
+   if (device->physical_device->use_fmask) {
       nir_tex_instr *tex_all_same = nir_tex_instr_create(b->shader, 2);
       tex_all_same->sampler_dim = GLSL_SAMPLER_DIM_MS;
       tex_all_same->op = nir_texop_samples_identical;
@@ -671,7 +671,7 @@ radv_meta_build_resolve_shader_core(nir_builder *b, bool is_integer, int samples
    tmp = nir_fdiv(b, tmp, nir_imm_float(b, samples));
    nir_store_var(b, color, tmp, 0xf);
 
-   if (gfx_level < GFX11) {
+   if (device->physical_device->use_fmask) {
       nir_push_else(b, NULL);
       nir_store_var(b, color, &tex->dest.ssa, 0xf);
       nir_pop_if(b, NULL);

src/amd/vulkan/radv_meta.h

@@ -266,9 +266,9 @@ nir_builder PRINTFLIKE(3, 4)
 nir_shader *radv_meta_build_nir_vs_generate_vertices(struct radv_device *dev);
 nir_shader *radv_meta_build_nir_fs_noop(struct radv_device *dev);
 
-void radv_meta_build_resolve_shader_core(nir_builder *b, bool is_integer, int samples,
+void radv_meta_build_resolve_shader_core(struct radv_device *device, nir_builder *b, bool is_integer,
-                                         nir_variable *input_img, nir_variable *color,
+                                         int samples, nir_variable *input_img, nir_variable *color,
-                                         nir_ssa_def *img_coord, enum amd_gfx_level gfx_level);
+                                         nir_ssa_def *img_coord);
 
 nir_ssa_def *radv_meta_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding);
 

src/amd/vulkan/radv_meta_resolve_cs.c

@@ -88,8 +88,7 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
 
    nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
 
-   radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img, color, src_coord,
+   radv_meta_build_resolve_shader_core(dev, &b, is_integer, samples, input_img, color, src_coord);
-                                       dev->physical_device->rad_info.gfx_level);
 
    nir_ssa_def *outval = nir_load_var(&b, color);
    if (is_srgb)

src/amd/vulkan/radv_meta_resolve_fs.c

@@ -56,8 +56,7 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samp
    nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, src_offset), 0x3);
    nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
 
-   radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img, color, img_coord,
+   radv_meta_build_resolve_shader_core(dev, &b, is_integer, samples, input_img, color, img_coord);
-                                       dev->physical_device->rad_info.gfx_level);
 
    nir_ssa_def *outval = nir_load_var(&b, color);
    nir_store_var(&b, color_out, outval, 0xf);

src/amd/vulkan/radv_pipeline.c

@@ -281,6 +281,8 @@ radv_get_hash_flags(const struct radv_device *device, bool stats)
       hash_flags |= RADV_HASH_SHADER_ROBUST_BUFFER_ACCESS2;
    if (device->instance->debug_flags & RADV_DEBUG_SPLIT_FMA)
       hash_flags |= RADV_HASH_SHADER_SPLIT_FMA;
+   if (device->instance->debug_flags & RADV_DEBUG_NO_FMASK)
+      hash_flags |= RADV_HASH_SHADER_NO_FMASK;
    return hash_flags;
 }
 

src/amd/vulkan/radv_private.h

@@ -281,6 +281,9 @@ struct radv_physical_device {
    /* Whether DCC should be enabled for MSAA textures. */
    bool dcc_msaa_allowed;
 
+   /* Whether to enable FMASK compression for MSAA textures (GFX6-GFX10.3) */
+   bool use_fmask;
+
    /* Whether to enable NGG. */
    bool use_ngg;
 
@@ -1918,6 +1921,7 @@ struct radv_event {
 #define RADV_HASH_SHADER_EMULATE_RT            (1 << 16)
 #define RADV_HASH_SHADER_SPLIT_FMA             (1 << 17)
 #define RADV_HASH_SHADER_RT_WAVE64             (1 << 18)
+#define RADV_HASH_SHADER_NO_FMASK              (1 << 19)
 
 struct radv_pipeline_key;
 

src/amd/vulkan/radv_shader.c

@@ -997,7 +997,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_
       .lower_txf_offset = true,
       .lower_tg4_offsets = true,
       .lower_txs_cube_array = true,
-      .lower_to_fragment_fetch_amd = device->physical_device->rad_info.gfx_level < GFX11,
+      .lower_to_fragment_fetch_amd = device->physical_device->use_fmask,
       .lower_lod_zero_width = true,
       .lower_invalid_implicit_lod = true,
       .lower_array_layer_round_even = true,