radeonsi: move VS_STATE.LS_OUT_PATCH_SIZE a few bits higher to make space there
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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@@ -238,7 +238,7 @@ static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
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static LLVMValueRef
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get_tcs_in_patch_stride(struct si_shader_context *ctx)
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{
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return si_unpack_param(ctx, ctx->vs_state_bits, 8, 13);
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return si_unpack_param(ctx, ctx->vs_state_bits, 11, 13);
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}
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static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
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@@ -256,8 +256,8 @@ enum {
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#define C_VS_STATE_PROVOKING_VTX_INDEX 0xFFFFFFCF
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#define S_VS_STATE_STREAMOUT_QUERY_ENABLED(x) (((unsigned)(x) & 0x1) << 6)
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#define C_VS_STATE_STREAMOUT_QUERY_ENABLED 0xFFFFFFBF
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#define S_VS_STATE_LS_OUT_PATCH_SIZE(x) (((unsigned)(x) & 0x1FFF) << 8)
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#define C_VS_STATE_LS_OUT_PATCH_SIZE 0xFFE000FF
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#define S_VS_STATE_LS_OUT_PATCH_SIZE(x) (((unsigned)(x) & 0x1FFF) << 11)
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#define C_VS_STATE_LS_OUT_PATCH_SIZE 0xFF0007FF
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#define S_VS_STATE_LS_OUT_VERTEX_SIZE(x) (((unsigned)(x) & 0xFF) << 24)
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#define C_VS_STATE_LS_OUT_VERTEX_SIZE 0x00FFFFFF
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@@ -95,8 +95,11 @@ struct si_shader_context {
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/* VS states and layout of LS outputs / TCS inputs at the end
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* [0] = clamp vertex color
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* [1] = indexed
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* [8:20] = stride between patches in DW = num_inputs * num_vertices * 4
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* max = 32*32*4 + 32*4
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* [2:3] = NGG: output primitive type
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* [4:5] = NGG: provoking vertex index
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* [6] = NGG: streamout queries enabled
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* [11:23] = stride between patches in DW = num_inputs * num_vertices * 4
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* max = 32*32*4 + 32*4
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* [24:31] = stride between vertices in DW = num_inputs * 4
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* max = 32*4
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*/
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