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ac,radv,radeonsi: move ZRANGE_PRECISION to mutable DS fields

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The DS surfaces are now completely configured in common code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29349>
This commit is contained in:
Samuel Pitoiset
2024-05-23 16:01:27 +02:00
committed by Marge Bot
parent 332a06903d
commit cd5f980d51
4 changed files with 19 additions and 19 deletions
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8
src/amd/common/ac_descriptors.c
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@@ -609,8 +609,7 @@ ac_init_gfx6_ds_surface(const struct radeon_info *info, const struct ac_ds_state
S_028008_Z_READ_ONLY(state->z_read_only) | S_028008_Z_READ_ONLY(state->z_read_only) |
S_028008_STENCIL_READ_ONLY(state->stencil_read_only); S_028008_STENCIL_READ_ONLY(state->stencil_read_only);
ds->db_z_info = S_028040_FORMAT(db_format) | ds->db_z_info = S_028040_FORMAT(db_format) |
S_028040_NUM_SAMPLES(util_logbase2(state->num_samples)) | S_028040_NUM_SAMPLES(util_logbase2(state->num_samples));
S_028040_ZRANGE_PRECISION(state->zrange_precision);
ds->db_stencil_info = S_028044_FORMAT(stencil_format); ds->db_stencil_info = S_028044_FORMAT(stencil_format);
if (info->gfx_level >= GFX7) { if (info->gfx_level >= GFX7) {
@@ -699,7 +698,6 @@ ac_init_gfx9_ds_surface(const struct radeon_info *info, const struct ac_ds_state
S_028038_NUM_SAMPLES(util_logbase2(state->num_samples)) | S_028038_NUM_SAMPLES(util_logbase2(state->num_samples)) |
S_028038_SW_MODE(surf->u.gfx9.swizzle_mode) | S_028038_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028038_MAXMIP(state->num_levels - 1) | S_028038_MAXMIP(state->num_levels - 1) |
S_028038_ZRANGE_PRECISION(state->zrange_precision) |
S_028040_ITERATE_256(info->gfx_level >= GFX11); S_028040_ITERATE_256(info->gfx_level >= GFX11);
ds->db_stencil_info = S_02803C_FORMAT(stencil_format) | ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
S_02803C_SW_MODE(surf->u.gfx9.zs.stencil_swizzle_mode) | S_02803C_SW_MODE(surf->u.gfx9.zs.stencil_swizzle_mode) |
@@ -881,6 +879,8 @@ ac_set_mutable_ds_surface_fields(const struct radeon_info *info, const struct ac
ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1); ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
} }
} }
ds->db_z_info |= S_028038_ZRANGE_PRECISION(state->zrange_precision);
} else { } else {
if (state->tc_compat_htile_enabled) { if (state->tc_compat_htile_enabled) {
ds->u.gfx6.db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); ds->u.gfx6.db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
@@ -888,5 +888,7 @@ ac_set_mutable_ds_surface_fields(const struct radeon_info *info, const struct ac
} else { } else {
ds->u.gfx6.db_depth_info |= S_02803C_ADDR5_SWIZZLE_MASK(1); ds->u.gfx6.db_depth_info |= S_02803C_ADDR5_SWIZZLE_MASK(1);
} }
ds->db_z_info |= S_028040_ZRANGE_PRECISION(state->zrange_precision);
} }
} }

2
src/amd/common/ac_descriptors.h
View File

@@ -142,7 +142,6 @@ struct ac_ds_state {
uint32_t first_layer : 14; uint32_t first_layer : 14;
uint32_t last_layer : 14; uint32_t last_layer : 14;
uint32_t zrange_precision : 1;
uint32_t allow_expclear : 1; uint32_t allow_expclear : 1;
uint32_t stencil_only : 1; uint32_t stencil_only : 1;
uint32_t z_read_only : 1; uint32_t z_read_only : 1;
@@ -190,6 +189,7 @@ struct ac_mutable_ds_state {
const struct ac_ds_surface *ds; /* original DS surface */ const struct ac_ds_surface *ds; /* original DS surface */
enum pipe_format format; enum pipe_format format;
uint32_t tc_compat_htile_enabled : 1; uint32_t tc_compat_htile_enabled : 1;
uint32_t zrange_precision : 1;
uint32_t no_d16_compression : 1; uint32_t no_d16_compression : 1;
}; };

2
src/amd/vulkan/radv_device.c
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@@ -1850,7 +1850,6 @@ radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buff
.num_samples = iview->image->vk.samples, .num_samples = iview->image->vk.samples,
.first_layer = iview->vk.base_array_layer, .first_layer = iview->vk.base_array_layer,
.last_layer = max_slice, .last_layer = max_slice,
.zrange_precision = true,
.stencil_only = stencil_only, .stencil_only = stencil_only,
.z_read_only = !(ds_aspects & VK_IMAGE_ASPECT_DEPTH_BIT), .z_read_only = !(ds_aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
.stencil_read_only = !(ds_aspects & VK_IMAGE_ASPECT_STENCIL_BIT), .stencil_read_only = !(ds_aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
@@ -1865,6 +1864,7 @@ radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buff
.ds = &ds->ac, .ds = &ds->ac,
.format = vk_format_to_pipe_format(iview->image->vk.format), .format = vk_format_to_pipe_format(iview->image->vk.format),
.tc_compat_htile_enabled = radv_htile_enabled(iview->image, level) && radv_image_is_tc_compat_htile(iview->image), .tc_compat_htile_enabled = radv_htile_enabled(iview->image, level) && radv_image_is_tc_compat_htile(iview->image),
.zrange_precision = true,
.no_d16_compression = true, .no_d16_compression = true,
}; };

26
src/gallium/drivers/radeonsi/si_state.c
View File

@@ -3522,18 +3522,19 @@ static void gfx6_emit_framebuffer_state(struct si_context *sctx, unsigned index)
(zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
: RADEON_PRIO_DEPTH_BUFFER)); : RADEON_PRIO_DEPTH_BUFFER));
const unsigned level = zb->base.u.tex.level;
/* Set mutable fields. */ /* Set mutable fields. */
const struct ac_mutable_ds_state mutable_ds_state = { const struct ac_mutable_ds_state mutable_ds_state = {
.ds = &zb->ds, .ds = &zb->ds,
.format = tex->db_render_format, .format = tex->db_render_format,
.tc_compat_htile_enabled = vi_tc_compat_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS), .tc_compat_htile_enabled = vi_tc_compat_htile_enabled(tex, level, PIPE_MASK_ZS),
.zrange_precision = tex->depth_clear_value[level] != 0,
}; };
struct ac_ds_surface ds; struct ac_ds_surface ds;
ac_set_mutable_ds_surface_fields(&sctx->screen->info, &mutable_ds_state, &ds); ac_set_mutable_ds_surface_fields(&sctx->screen->info, &mutable_ds_state, &ds);
unsigned level = zb->base.u.tex.level;
if (sctx->gfx_level >= GFX10) { if (sctx->gfx_level >= GFX10) {
radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, ds.u.gfx6.db_htile_data_base); radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, ds.u.gfx6.db_htile_data_base);
radeon_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, ds.db_depth_size); radeon_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, ds.db_depth_size);
@@ -3544,8 +3545,7 @@ static void gfx6_emit_framebuffer_state(struct si_context *sctx, unsigned index)
radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 7); radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 7);
radeon_emit(S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */ radeon_emit(S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
} }
radeon_emit(ds.db_z_info | /* DB_Z_INFO */ radeon_emit(ds.db_z_info); /* DB_Z_INFO */
S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */ radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */
radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */ radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */
radeon_emit(ds.db_stencil_base); /* DB_STENCIL_READ_BASE */ radeon_emit(ds.db_stencil_base); /* DB_STENCIL_READ_BASE */
@@ -3565,8 +3565,7 @@ static void gfx6_emit_framebuffer_state(struct si_context *sctx, unsigned index)
radeon_emit(ds.db_depth_size); /* DB_DEPTH_SIZE */ radeon_emit(ds.db_depth_size); /* DB_DEPTH_SIZE */
radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 10); radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 10);
radeon_emit(ds.db_z_info | /* DB_Z_INFO */ radeon_emit(ds.db_z_info); /* DB_Z_INFO */
S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */ radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */
radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */ radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */
radeon_emit(S_028044_BASE_HI(ds.db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */ radeon_emit(S_028044_BASE_HI(ds.db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
@@ -3586,8 +3585,7 @@ static void gfx6_emit_framebuffer_state(struct si_context *sctx, unsigned index)
radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 9); radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 9);
radeon_emit(ds.u.gfx6.db_depth_info); /* DB_DEPTH_INFO */ radeon_emit(ds.u.gfx6.db_depth_info); /* DB_DEPTH_INFO */
radeon_emit(ds.db_z_info | /* DB_Z_INFO */ radeon_emit(ds.db_z_info); /* DB_Z_INFO */
S_028040_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */ radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */
radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */ radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */
radeon_emit(ds.db_stencil_base); /* DB_STENCIL_READ_BASE */ radeon_emit(ds.db_stencil_base); /* DB_STENCIL_READ_BASE */
@@ -3744,22 +3742,22 @@ static void gfx11_dgpu_emit_framebuffer_state(struct si_context *sctx, unsigned
(zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
: RADEON_PRIO_DEPTH_BUFFER)); : RADEON_PRIO_DEPTH_BUFFER));
const unsigned level = zb->base.u.tex.level;
/* Set mutable fields. */ /* Set mutable fields. */
const struct ac_mutable_ds_state mutable_ds_state = { const struct ac_mutable_ds_state mutable_ds_state = {
.ds = &zb->ds, .ds = &zb->ds,
.format = tex->db_render_format, .format = tex->db_render_format,
.tc_compat_htile_enabled = vi_tc_compat_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS), .tc_compat_htile_enabled = vi_tc_compat_htile_enabled(tex, level, PIPE_MASK_ZS),
.zrange_precision = tex->depth_clear_value[level] != 0,
}; };
struct ac_ds_surface ds; struct ac_ds_surface ds;
ac_set_mutable_ds_surface_fields(&sctx->screen->info, &mutable_ds_state, &ds); ac_set_mutable_ds_surface_fields(&sctx->screen->info, &mutable_ds_state, &ds);
unsigned level = zb->base.u.tex.level;
gfx11_set_context_reg(R_028014_DB_HTILE_DATA_BASE, ds.u.gfx6.db_htile_data_base); gfx11_set_context_reg(R_028014_DB_HTILE_DATA_BASE, ds.u.gfx6.db_htile_data_base);
gfx11_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, ds.db_depth_size); gfx11_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, ds.db_depth_size);
gfx11_set_context_reg(R_028040_DB_Z_INFO, ds.db_z_info | gfx11_set_context_reg(R_028040_DB_Z_INFO, ds.db_z_info);
S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
gfx11_set_context_reg(R_028044_DB_STENCIL_INFO, ds.db_stencil_info); gfx11_set_context_reg(R_028044_DB_STENCIL_INFO, ds.db_stencil_info);
gfx11_set_context_reg(R_028048_DB_Z_READ_BASE, ds.db_depth_base); gfx11_set_context_reg(R_028048_DB_Z_READ_BASE, ds.db_depth_base);
gfx11_set_context_reg(R_02804C_DB_STENCIL_READ_BASE, ds.db_stencil_base); gfx11_set_context_reg(R_02804C_DB_STENCIL_READ_BASE, ds.db_stencil_base);