freedreno: Fully define a730 and a740 device properties

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
This commit is contained in:
Danylo Piliaiev
2023-04-17 15:38:00 +02:00
committed by Marge Bot
parent a70e04b0c0
commit cd3719be7d

View File

@@ -683,10 +683,8 @@ add_gpus([
)
))
# Minimal definition needed for ir3 assembler/disassembler
add_gpus([
GPUId(730),
GPUId(740),
GPUId(chip_id=0x07030001, name="FD730"),
], A6xxGPUInfo(
CHIP.A7XX,
a6xx_gen4,
@@ -697,7 +695,108 @@ add_gpus([
cs_shared_mem_size = 32 * 1024,
wave_granularity = 2,
fibers_per_sp = 128 * 2 * 16,
magic_regs = dict()
magic_regs = dict(
# PC_POWER_CNTL = 7,
TPL1_DBG_ECO_CNTL = 0x1000000,
GRAS_DBG_ECO_CNTL = 0x800,
SP_CHICKEN_BITS = 0x1440,
UCHE_CLIENT_PF = 0x00000084,
PC_MODE_CNTL = 0x0000003f, # 0x00001f1f in some tests
SP_DBG_ECO_CNTL = 0x10000000,
RB_DBG_ECO_CNTL = 0x00000000,
RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed?
# HLSQ_DBG_ECO_CNTL = 0x0,
RB_UNKNOWN_8E01 = 0x0,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x3200000
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00840004],
[A6XXRegs.REG_A6XX_TPL1_UNKNOWN_B602, 0x00000724],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00002400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE0A, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000040],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6C, 0x00008000],
[A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x20080000],
[A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21fc7f00],
[A6XXRegs.REG_A7XX_VFD_UNKNOWN_A600, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE73, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
],
))
add_gpus([
GPUId(740), # Deprecated, used for dev kernels.
GPUId(chip_id=0x43050a01, name="FD740"),
], A6xxGPUInfo(
CHIP.A7XX,
a6xx_gen4,
num_ccu = 6,
tile_align_w = 64,
tile_align_h = 32,
num_vsc_pipes = 32,
cs_shared_mem_size = 32 * 1024,
wave_granularity = 2,
fibers_per_sp = 128 * 2 * 16,
magic_regs = dict(
# PC_POWER_CNTL = 7,
TPL1_DBG_ECO_CNTL = 0x11100000,
GRAS_DBG_ECO_CNTL = 0x00004800,
SP_CHICKEN_BITS = 0x10001400,
UCHE_CLIENT_PF = 0x00000084,
# Blob uses 0x1f or 0x1f1f, however these values cause vertices
# corruption in some tests.
PC_MODE_CNTL = 0x0000003f,
SP_DBG_ECO_CNTL = 0x10000000,
RB_DBG_ECO_CNTL = 0x00000000,
RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed?
# HLSQ_DBG_ECO_CNTL = 0x0,
RB_UNKNOWN_8E01 = 0x0,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000000
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004],
[A6XXRegs.REG_A6XX_TPL1_UNKNOWN_B602, 0x00000724],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00000400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00430800],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE0A, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6C, 0x00000000],
[A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000],
[A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21585600],
[A6XXRegs.REG_A7XX_VFD_UNKNOWN_A600, 0x00008000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE73, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8009, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800A, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000],
],
))
template = """\