radv: emit PA_SU_PRIM_FILTER_CNTL in the graphics preamble
This register doesn't change. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19654>
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cd2e2021a0
@@ -4379,19 +4379,9 @@ static void
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radv_pipeline_emit_multisample_state(struct radeon_cmdbuf *ctx_cs,
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const struct radv_graphics_pipeline *pipeline)
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{
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const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
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const struct radv_multisample_state *ms = &pipeline->ms;
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radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
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/* The exclusion bits can be set to improve rasterization efficiency
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* if no sample lies on the pixel boundary (-8 sample offset). It's
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* currently always TRUE because the driver doesn't support 16 samples.
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*/
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bool exclusion = pdevice->rad_info.gfx_level >= GFX7;
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radeon_set_context_reg(
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ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
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S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
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}
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static void
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@@ -630,6 +630,15 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
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radeon_set_uconfig_reg(cs, R_031114_SPI_GS_THROTTLE_CNTL2, 0x1544D);
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}
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/* The exclusion bits can be set to improve rasterization efficiency if no sample lies on the
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* pixel boundary (-8 sample offset). It's currently always TRUE because the driver doesn't
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* support 16 samples.
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*/
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bool exclusion = physical_device->rad_info.gfx_level >= GFX7;
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radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
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S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
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S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
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si_emit_compute(device, cs);
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}
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